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| 型號： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 31/69頁 |
| 文件大小： | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
37
www.emmicroelectronic.com
9. Millisecond Counter
The EM6821 has a built-in millisecond binary coded decimal counter. It can be used to measure the time
elapsed between two events (hardware or software events). With a system clock of 32kHz, the counter
generates every 1/10 second or every second an interrupt request.
The counter value read on registers RegMSCDataL, RegMSCDataM and RegMSCDataH is in binary coded
decimal format (000 to 999). To maintain the data integrity for the 3 decimal digits inside BCD[11:0] one must
stop the counter while reading the full 3 digit value.
An overflow flag FlSec is set whenever the counter reached 999. This flag is helpful when the counter is used in
polling mode and twice the same value is read. In this case, if the flag is set to 1, it indicates that the two
readings were 1 second apart, in the case the flag is not set, the two readings must have been very short one
after the other. After every read of RegMSCCntl2 the FlSec gets automatically reset.
The millisecond counter is reset with every system reset. Setting the ResMSC flag located in register
RegMSCCntl1
resets the counter value only. This flag is automatically reset after the write operation. For good
resolution in Pa3-mode use the Ck[14 ] debouncer clock (250us). Or if the 1/1000 sec is not relevant then
choose Ck[10] (4ms) as debouncer clock. Doing so will save power. The debouncer selection is made in
register RegMSCCntl2 bit DebFreqSel.
Changing PA3Edge while RunEn=1 or PA3/up=1 may generate a MSC event (start or stop). This behavior is
useful for the - CPU controlled start and PA3 controlled stop - mode, But in general one does all the setup
before starting the counter.
9.1 PA[3] Input for MSC
In hardware Start/Stop mode the counter is triggered with the port A terminal PA[3] input. In this case PA[3] is
debounced with the prescaler Ck[14] (or Ck[10]) clock. The triggering edge selection is made with bit PA3Edge
in register RegMSCCntl2 (default negative edge). The PA[3] input for the millisecond counter is totally
independent of the PA[3] interrupt edge selection and the PA[3] polarity selection for the 10 bit counter.
However the pull-up or pull-down selection is common to all peripheries sharing the port A.
9.2 IRQ from MSC
An Interrupt request IRQMSC is send on either every 1/10 seconds or every second, depending on the bit
IntSel
in register RegMSCCntl2. For interrupt handling please refer to the interrupt control section.
Figure 27. MSC Block Diagram
RegMSCCntl1,2
PA3
Debouncer
EN
IRQMSC
RunEn
PA3/uP
dT/MSC
Data Bus
Data
IntSel
1 Sec
1/10 Sec
Ck[10]
Ck[14
PA[3]
Terminal
PA3Internal
NegEdg
PosEdg
1
0
PA3Edge
0
1
0
1
4
CK1000
FlSecl
DebFreqSel
Start/Stop
Control
dT/MSC
BCD
1/1000
Sec
BCD
1/100
Sec
BCD
1/10
Sec
This signal used
as reference in
text description
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