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參數(shù)資料
| 型號(hào)： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 18/69頁(yè) |
| 文件大?。?/td> | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
25
www.emmicroelectronic.com
6.7 Serial Interface Registers
Table 6.7.1 Register RegSCntl1
Bit
Name
Reset
R/W
Description
3
MS1
0
R/W
Frequency selection
2
MS0
0
R/W
Frequency selection
1
POSnNeg
0
R/W
Positive or negative clock edge selection for
shift operation
0
MSBnLSB
0
R/W
Shift MSB or LSB value first
Default "0" is: Slave mode external clock, negative edge, LSB first
Table 6.7.2 Frequency and Master Slave Mode Selection
MS1
MS0
Description
0
Slave mode: Clock from external
0
1
Master mode: System clock / 4
1
0
Master mode: System clock / 2
1
Master mode: System clock
Table 6.7.3 Register RegSCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Enabling the interface,
2
Status
0
R/W
Ready or Chip Select output on PSP[1]
1
OM[1]
0
R/W
Output mode select 1
0
OM[0]
0
R/W
Output mode select 0
Default "0" is: Interface disabled, status 0, serial mode, output tristate.
Table 6.7.4 Register RegSDataL
Bit
Name
Reset
R/W
Description
3
SerDataL[3]
0
R/W
Serial data low nibble
2
SerDataL[2]
0
R/W
Serial data low nibble
1
SerDataL[1]
0
R/W
Serial data low nibble
0
SerDataL[0]
0
R/W
Serial data low nibble
Default "0" is: Data equal 0.
Table 6.7.5 Register RegSDataH
Bit
Name
Reset
R/W
Description
3
SerDataH[3]
0
R/W
Serial data high nibble
2
SerDataH[2]
0
R/W
Serial data high nibble
1
SerDataH[1]
0
R/W
Serial data high nibble
0
SerDataH[0]
0
R/W
Serial data high nibble
Default "0" is: Data equal 0.
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