參數(shù)資料
型號(hào)： EM6821TQ52B
英文描述： Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-EPSOIC
中文描述： 微控制器
文件頁(yè)數(shù)： 26/69頁(yè)
文件大?。?/td> 852K
代理商： EM6821TQ52B
EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
32
www.emmicroelectronic.com
8.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits CountFSel2…0 in
register RegCCntl1. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock
frequency for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over
can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little as 977
s (Ck[15], 4 bit length). The
IRQCount0
, generated at each roll over, can be used for time bases, measurements length definitions, input
polling, wake up from Halt mode, etc. The IRQCount0 and IRQComp are generated with the system clock
Ck[16] rising edge. IRQCount0 condition in up count mode is : reaching 3FF if 10-bit counter length (or FF, 3F,
F in 8, 6, 4-bit counter length). In down count mode the condition is reaching ‘0’. The non-selected bits are ‘don’t
care’. For IRQComp refer to section 8.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with P commands using for instance the prescaler reset
function.
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to the Figure 10 on page
14 for details. Both sources can be either debounced (Ck[11] or Ck[8]) or direct inputs, the input polarity can
also be chosen. The output after the debouncer polarity selector is named PA3 , PA0 respectively.
For the
debouncer and input polarity selection refer to chapter 6.3.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6821 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input). Maximum
port A input frequency is limited to 200kHz (@VDD
≥ 1.5 V). If higher frequencies are needed, please contact
EM-Marin.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1
bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit EvCount) is chosen. Refer also to Figure 24.
Internal Clock Synchronization.
Figure 23. Counter Clock Timing
P re s c a le r F requ enc ie s or D ebo unc ed P o rt A C loc k s
N on-D e b ounc ed P o rt A C lo cks (S ys te m C lo ck In d e pende nt)
S yste m C lo c k
P re sca le r C lo c k
C ountin g
C ounter IR Q ’s
D iv ided C loc k
S yste m C lo c k
Po rt A C lo c k
C ountin g
C o unter IR Q ’s
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