- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384295 > EM6124 (Electronic Theatre Controls, Inc.) Digitally Programmable 8 to 25 Multiplex LCD Controller & Driver PDF資料下載
參數(shù)資料
| 型號： | EM6124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Programmable 8 to 25 Multiplex LCD Controller & Driver |
| 中文描述： | 數(shù)字可編程8至25多路LCD控制器 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 1900K |
| 代理商： | EM6124 |
EM6124
Pin Assignment
Name
S1...S121
FR
DI
DO
CLK
RES1
RES2
V
LCD
V
DD1
V
DD2
V
HV
V
SS
Function
LCD outputs, see Fig.4
AC I/O signal for LCD driver output
Serial data input
Serial data output
Data clock input
General reset
Reset the serial interface counter
Internal generated voltage output
Power supply for logic
Power supply for analogic
Power supply for high voltage
Supply GND
Ta ble 9
1 Bit Interface Description
This 1 bit in er ace is very sim ple to use. There are three
modes to load data into the EM6124.
Com mand byte only mode
To validate this mode, 8 bits must be shifted with bit 3 to bit
7 setted to 1L. This mode is used for blank, set or sleep
mode func ions.
Com mand byte and ini ial za ion mode
To validate this mode, 32 bits must be shifted with bit 0 and
bit 1 setted to 1L. Bit 2 (sleep) can be ac ive or in ac ive. Bit
3 to bit 7 (RAM ad dress) can be in any state but it is im por
tant that they are not all si mul a neously setted to 1L, oth er
wise the chip will be in com mand byte only mode.
Com mand byte and dis play in or ma ion mode
To validate this mode, 128 bits must be shifted, eight first
bits are for com mand byte, all the other are RAM data de
pend ng of col bit mode and mul i plex ra io. There are also
x bits don’t care in each load ng de pend ng on the
programmation of the chip (see Fig. 4 for more de ails).
In each RAM’s data load ng, the com mand byte has to be
in ro duced for the RAM ad dress. Be ore load ng any data
into the RAM the chip has to be in ial zed.
Com mand Byte
Commmand Bits 0 to 7
0
1
2
3
Blank
Set
Sleep
4
RAM ad dress
5
6
7
Ta ble 6
Cmdbit 0
: Blank bit forces all col umn out puts off.
Cmdbit 1:
Set bit forces all col umn out put on.
Note: If bit 0 and bit 1 are both to 1L, the chip will be in ini ial
iza ion mode. See re marks be ow.
Cmdbit 2
: Sleep mode bit, stops the volt age booster and the
in er nal os cil a or, ac ive bit col forces all out puts to V
SS
.
Cmdbits 3-7
: RAM ad dress bits. See ta ble 6.
If Cmdbits 3-7 are set to 1L, EM6124 is in Cmd byte only mode.
Initialization Bits
Ini ial za ion Bits 8 to 15
8
9
10
11
12
Mux Mode Temp. Coeff.
Checker Inv.Checker
Ini ial za ion Bits 16 to 23
16
17
18
19
M/LSB
Video
Step 1 Step 2 Step 3
Ini ial za ion Bits 24 to 31
24
25
26
27
Icon
Sleep 2 Test 6
Test 5
13
14
Col
15
Inv.Row
20
21
22
23
Step 4 Step 5 Step 6
28
29
30
31
Test 4
Test 3
Test 2
Test 1
Ta ble 7
Mux ra io (Init. bit 8, 9)
8
9
0
0
0
1
1
0
1
1
Ta ble 8
mux mode
8
16
20
24
Init.bit 8-9:
Mux mode bits. The mul i plex ra io is se ected by
these two bits. Ta ble 8 shows the cor e spond ng val ues.
Init.bit 10-11
: V
LCD
tem per a ure co ef i cient is se ected by these
two bits. Ta ble 11 shows the cor e spond ng val ues.
I
nit.bit 12
: Checker bit gives the pos si bil ty to force all out puts
seg ments in checked form (see Fig. 10 and Fig. 18.14).
Init.bit 13
: In verse Checker bit gives the pos si bil ty to force all
out puts seg ments in in verse checked form (see Fig. 10 and
Fig. 18.15).
Init.bit 14
: Col bit configures the EM6124 on row and col umn
driver or col umn driver only. In this mode the frame fre quency
must be ex er nal.
Init.bit 15
: Row in ver sion, pos si bil ty to in verse the or der of the
row out puts (see Ta ble 10 and Fig. 18.12).
Init.bit 16
: M/LSB, pos si bil ty to in verse the or der load ng for
RAM data (see Fig. 4).
Init.bit 17
: Video bit, pos si bil ty to in verse the con ent of the
RAM. All the 0L pass to 1L and all the 1L pass to 0L (see Fig.
18.11).
Init.bit 18-23
: V
LCD
64 steps programmation bits. See Fig. 8.
Bit 18 (step 1) for MSB and bit 23 (step 6) for LSB.
Init.bit 24
: Icon bit adds one line more to the se ected mux
mode ra io for icon seg ments out puts.
Init.bit 25
:
Sleep 2. Set all out puts at V
SS
.
Init.bit 26-31
: Must be setted to 0L.
Re set 1
Power-up
: Must be fol owed by a RESET cy cle. After the
re set 1 pulse the LCD con rol er driver is set to the fol ow
ing sta us:
- All out puts at V
- Blank & Set (cmdbits 0,1) = 0L
- Sleep mode (cmdbit 2) = 0L
- RAM ad dress (cmdbits 3 to 7) = 0L
- Mul i plex ra io (init.bits 8, 9) = 0L
- Tem per a ure co ef i cient (init.bits 10,11) = 0L
- Checker & Inv.Checker (init.bits 12, 13) = 0L
- Col Mode (init.bit 14) = 1L
- Inv. Row (init.bit 15) = 0L
- M/LSB (init.bit 16) = 1L
- Video (init.bit 17) = 1L
- V
step (init.bits 18 to 23) = 0L
- Icon (init.bit 24) = 0L
- Sleep 2 (init.bit 25) = 1L
- The con ent of the RAM re mains un changed
An ini ial za ion should take place af er re set (32 bits sent).
4
相關PDF資料 |
PDF描述 |
|---|---|
| EM614163 | 256K x 16 High Speed EDO DRAM |
| EM614163A | 256K x 16 High Speed EDO DRAM |
| EM614163A-30 | 256K x 16 High Speed EDO DRAM |
| EM614163A-35 | 256K x 16 High Speed EDO DRAM |
| EM614163A-40 | 256K x 16 High Speed EDO DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EM614163A-50 | 制造商:ETRON 功能描述: |
| EM620F32-45LF | 制造商:EMLSI 制造商全稱:Emerging Memory & Logic Solutions Inc 功能描述:256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| EM620F32-45LL | 制造商:EMLSI 制造商全稱:Emerging Memory & Logic Solutions Inc 功能描述:256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| EM620F32-85LF | 制造商:EMLSI 制造商全稱:Emerging Memory & Logic Solutions Inc 功能描述:256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| EM620F32-85LL | 制造商:EMLSI 制造商全稱:Emerging Memory & Logic Solutions Inc 功能描述:256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。