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參數(shù)資料
| 型號(hào)： | EM6124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Programmable 8 to 25 Multiplex LCD Controller & Driver |
| 中文描述： | 數(shù)字可編程8至25多路LCD控制器 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 1900K |
| 代理商： | EM6124 |
EM6124
15
Functional Description
Supply Voltage V
DD1
, V
DD2
, VH
V
, V
LCD
, V
SS
The volt age be ween V
and V
is the sup ply volt age for
the logic and the in er ace. The volt age be ween V
and
V
is the sup ply volt age for the analogic. V
and V
must be the same volt age and, in or der to guar an ee the
best func ion ng, V
and V
have to be sep a ately con
nected to the PCB (see Fig. 19). The volt age V
is in er
nally gen er ated for the sup ply volt age of the LCD and is
used for the gen er a ion of the in er nal LCD bias level. An
ex er nal ca pac or of 1 μF must be con nected be ween
V
and V
. Ta ble 15 shows the re a ion ship be ween V1,
V2, V3, V4 for a pro grammed mul i plex rate. Note that V
> V1 > V2 > V3 > V
for the EM6124 8 mux pro
grammed, and for the EM6124 16, 20, 24 mux pro
grammed V
LCD
> V1 > V2 > V3 > V4 > V
. The volt age
be ween V
is the sup ply volt age for high volt age
part of the EM6124. An ex er nal V
may also be used by
con nect ng a power sup ply and pro gram ming a lower V
LCD
volt age dur ng ini ial za ion.
Data In put
The data in put pin, DI, is used to load se ial data into the
EM6124. The nor mal se ial data word length is128 bits. 32
and 8 bits are also avail able in a spe cial mode (see 1 Bit
In er ace De scrip ion). The com mand byte is loaded first
and then the seg ment data bits (see Fig. 4).
RES1 In put
Re set is ac com plished by ap ply ng an ex er nal RES1
pulse (ac ive low). When re set oc curs within the spec ied
time, all in er nal reg s er are re set how ever the con ent of
the RAM is still un changed. The state af er re set is de
scribed on page 4.
RES2 Input
Re set is ac com plished by ap ply ng an ex er nal RES2
pulse (ac ive low). When re set oc curs within the spec ied
time, the in er nal coun er for se ial in er ace is re set. The
coun er of the serial in er ace for data inputs is ready for a
new load ng of data. This re set 2 does not change the
con ent of the RAM nei her the con ent of the com mand
and the ini ial za ion bits. To avoid trou ble in case of soft
ware in er upt of the MPU dur ng data load ng, this func
tion can be used.
Power-Up
On power up the data in the shift reg s ers, the dis play
RAM, the se quencer driv ng the 8/16/20/24 rows and the
121 bit dis play latches are un de ined.
CLK In put
The clock in put is used to clock the DI se ial data into the
EM6124.
FR In put / Output
The frame fre quency is re al zed by an in er nal os cil a or
with a typ cal value of 75 Hz. The in er nal row fre quency
changes with the num ber of rows ( F
= 75 x n, where n
= 8, 16, 20, 24). When bit 14 (Col) is in ac ive (ac ive low),
the frame fre quency is given by the in er nal os cil a or. This
fre quency can be mea sured on the I/O FR. When bit 14
(Col) is ac ive (ac ive low), the frame fre quency is ex er nal
then the fre quency is given di ectly by the FR in put to the
row and col umn driver (see Fig. 16 and 17 for more de
tails con cern ng the frame fre quency).
Driver Out puts S1 to S116
There are 121 LCD driver out puts on the EM6124. The out
put as sign ments de pend on the cho sen mux mode ra io
(init. bits 8, 9) and the Col func ion (init. bit 14).
When init. bit 14 (Col) is ac ive, all 116 out puts func ion as
col umn driv ers. Ta ble “Out put Row As sign ments” and Fig.
4 de scribe ex actly the cor e spon dent data to the out put of
the chip. There is one to one re a ion ship be ween the dis
play RAM and the LCD driver out puts. Each pixel (seg
ment) driven by the EM6124 on the LCD has a dis play
RAM bit which cor e sponds to it. Set ing the bit turns the
pixel “on” and Clear ng it turns “off”.
For chip-on-glass better per or mances can be ob ained by cov er ng the back
side of the chip.
Typical Frame Frequency at V
DD
= 3 V
Typical Frame Frequency at T
A
= 25 °C
Fig.17.01
Fig.17.02
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