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參數(shù)資料
| 型號(hào)： | EM6124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Programmable 8 to 25 Multiplex LCD Controller & Driver |
| 中文描述： | 數(shù)字可編程8至25多路LCD控制器 |
| 文件頁(yè)數(shù)： | 2/23頁(yè) |
| 文件大小： | 1900K |
| 代理商： | EM6124 |
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Ab so ute Max mum Rat ngs
Parameter
Sup ply volt age range
Sup ply high volt age range
Internal generated V
Volt age at DI, DO, CLK, FR, RES
Volt age at S1 to S121
Stor age tem per a ure range
Elec ro static dis charge max.
to MIL-STD-883C method 3015
Max mum sol der ng con di ions
Symbol
V
DD1,2
V
HV
V
LCD
V
LOGIC
V
DISP
T
STO
Conditions
-0.3 V to 6 V
-0.3 V to 6 V
7 V
-0.3 V to V
DD
+0.3 V
-0.3 V to V
+0.3 V
-65 to +150 °C
V
Smax
T
Smax
1000 V
250 °C x 10 s
Ta ble 1
Stresses above these listed max mum rat ngs may cause
per ma nent dam age to the de vice. Ex po sure be yond
spec ied op er at ng con di ions may af ect de vice re i abil ty
or cause mal unc ion.
Han dling Pro ce dures
This de vice has built-in pro ec ion against high static volt
ages or elec ric fields; how ever, anti-static pre cau ions
must be taken as for any other CMOS com po nent. Un ess
oth er wise spec ied, proper op er a ion can only oc cur
when all ter mi nal volt ages are kept within the sup ply volt
age range. Un used in puts must al ways be tied to a de -
fined logic volt age level.
Op er ating Con di ions
Parameter
Symbol Min. Typ.Max. Unit
Operating temperature
Logic supply voltage
Supply high voltage
T
A
-40
2
2.5
+85
5.5
5.5
°C
V
V
V
DD1,2
V
HV
3
3
Ta ble 2
2
EM6124
Electrical Characteristics
V
DD1
= V
DD2
= 3 V, V
HV
= 2.5 to 5 V, and T
A
= -40 to +85 °C, un ess oth er wise spec ied
Pa am e er
Sym bol Test Con di ions
Min.
Typ.
Max.
Units
Standby sup ply cur ent
Standby sup ply cur ent
Dynamic supply current
Standby supply current
Sleep mode supply current
Sleep mode supply current
I
DD
I
HV
I
DD
I
HV
I
DD
I
HV
See note
1)
See note
1)
, V
LCD
step 30 (hexa)
See note
2)
See note
3)
, V
LCD
step 00 (hexa)
6
13
170
75
140
μA
μA
μA
μA
μA
μA
65
50
35
0.1
0.1
Con rol Sig nals DI, CLK, FR,
RES1,RES2
In put leak age
In put ca pac ance
Low level in put volt age
High level in put volt age
DC output component
V
LCD
(internally generated)
V
LCD
I
IN
C
IN
V
IL
V
± VDC
V
LCD
V
LCD
V
LCD
step
V
or V
at T
A
= 25 °C
-1
1
μA
pF
V
V
mV
8
0
0.3 V
DD1,2
V
100
0.7 V
DD1,2
See table 4
See note
4)
See note
5)
30
6.15
3 to 7
66
V
mV
1)
All out puts open, DI and CLK at V
, mux ra io = 24, checker pat ern.
Ta ble 3
2)
All out puts open, DI at V
SS
, f
CLK
= 1 MHz, mux ra io = 24, checker pat ern.
3)
DI and CLK at V
, checker pat ern, mux ra io = 8.
4)
Ini ial za ion bits 18 to 23 = 110000 and ini ial za ion bits 10, 11 = 00; la ser trim ming on re quest.
5)
Ini ial za ion bits 18 to 23 = 000000/111111.
DC Output Component
Output
Frame
n
n + 1
Logic Data
0L
0L
Measured*
| V
LCD
- V
1
|
| V
4
SS
|
Guaranteed
V
1
= 0.83 x V
LCD
± 100 mV
V
2
= 0.66 x V
LCD
± 100 mV
Row Driver
0L
0L
| V
LCD
- V
2
|
| V
3
- V
SS
|
V
3
= 0.34 x V
LCD
± 100 mV
V
4
= 0.17 x V
LCD
± 100 mV
Column Driver
n + 1
X
(load = -1 μA)
V
X
= ( load = +1 μA) + V
LCD
= 6 V, T
A
= 25 °C.
Test is per ormed for mul i plex rate = 25. All mul i plex rate
≠
25 are guar an eed by de sign. If mul i plex rate
≠
25, test will
be per ormed on re quest.
Ta ble 4
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