- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3799 > EFM32TG822F32 (Energy Micro)IC MCU 32BIT 32KB FLASH 48LQFP PDF資料下載
參數(shù)資料
| 型號： | EFM32TG822F32 |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 31/136頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 32KB FLASH 48LQFP |
| 特色產(chǎn)品： | EFM32 Tiny Gecko |
| 標準包裝： | 1 |
| 系列： | Tiny Gecko |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 32MHz |
| 連通性： | I²C，IrDA，智能卡，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x12b，D/A 1x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | 914-1031-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
126
www.energymicro.com
Implementation-specific
The behavior is not architecturally defined, and does not have to be
documented by individual implementations. Used when there are a number
of implementation options available and the option chosen does not affect
software compatibility.
Index register
In some load and store instruction descriptions, the value of this register
is used as an offset to be added to or subtracted from the base register
value to form the address that is sent to memory. Some addressing modes
optionally enable the index register value to be shifted prior to the addition
or subtraction.
See Also Base register.
Instruction cycle count
The number of cycles that an instruction occupies the Execute stage of the
pipeline.
Interrupt handler
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector
One of a number of fixed addresses in low memory, or in high memory if high
vectors are configured, that contains the first instruction of the corresponding
interrupt handler.
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word
are stored at increasing addresses in memory.
See Also Big-endian, Byte-invariant, Endianness.
Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the least significant byte within the
halfword at that address.
See Also Big-endian memory.
Load/store architecture
A processor architecture where data-processing operations only operate on
register contents, not directly on memory contents.
Memory Protection Unit
(MPU)
Hardware that controls access permissions to blocks of memory. An MPU
does not perform any address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to
fill up the pipeline before the preceding instructions have finished executing.
Prefetching an instruction does not mean that the instruction has to be
executed.
Read
Reads are defined as memory operations that have the semantics of a
load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB,
LDRB
, and POP.
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to
be defined by the implementation, or produces Unpredictable results if the
contents of the field are not zero. These fields are reserved for use in future
extensions of the architecture or are implementation#specific. All reserved
bits not used by the implementation must be written as 0 and read as 0.
Should Be One (SBO)
Write as 1, or all 1s for bit fields, by software. Writing as 0 produces
Unpredictable results.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC1313FHN33,551 | IC MCU 32BIT 32KB FLASH 33HVQFN |
| P80C32SBAA,512 | IC 80C51 MCU 8BIT ROMLESS 44PLCC |
| P80C32UBAA,512 | IC 80C51 MCU 8BIT ROMLESS 44PLCC |
| 1-5353583-1 | CONN RCPT 4X1 USB RT ANG SMD |
| 5353583-4 | CONN RCPT USB 4POS R/A SMD SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EFM32TG822F32-QFP48 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 48TQFP |
| EFM32TG822F32-QFP48T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG822F32-QFP48-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 48TQFP |
| EFM32-TG822F32-SK | 功能描述:IC MICRO KIT GECKO 48LQFP RoHS:是 類別:套件 >> 半導(dǎo)體產(chǎn)品 - IC 元件分類 系列:Tiny Gecko 其它有關(guān)文件:NXPLOGIC2-KIT-ND Contents 標準包裝:1 系列:74AUP 套件類型:邏輯 值:180 件 - 18 種值各 10 件 包裝:- 安裝類型:表面貼裝 包括封裝:6-XSON，8-XSON，8-XQFN 產(chǎn)品目錄頁面:2653 (CN2011-ZH PDF) 工具箱內(nèi)容:(10) 568-4391-1-ND - IC GATE MULT-FUNC CONFIG 6-XSON(10) 568-4390-1-ND - IC CONFIG MULT-FUNC GATE 6-XSON(10) 568-4389-1-ND - IC GATE DUAL FUNCTION 8-XSON(10) 568-4388-1-ND - IC GATE DUAL FUNCTION 8-XQFN(10) 568-4387-1-ND - IC F-F D-TYPE POS EDGE 8-XSON(10) 568-4386-1-ND - IC F-F D-TYPE POS EDGE 8-XQFN(10) 568-4385-1-ND - IC CONFIG MULTI-FUNC GATE 6-XSON(10) 568-4384-1-ND - IC EX-OR GATE 3-IN 6-XSON(10) 568-4383-1-ND - IC F-F D-TYPE POS EDGE 6-XSON(10) 568-4382-1-ND - IC LATCH D-TYPE 6-XSON更多... 其它名稱:NXPLOGIC2-KIT |
| EFM32TG822F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 48TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。