參數(shù)資料
型號： EFM32TG822F32
廠商： Energy Micro
文件頁數(shù)： 80/136頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1031-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
48
www.energymicro.com
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either
be signed or unsigned. See Section 3.3.5 (p. 42) .
Table 3.6 (p. 48) shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Table 3.6. Offset ranges
Instruction type
Immediate offset
Pre-indexed
Post-indexed
Word, halfword, signed
halfword, byte, or signed byte
#255 to 4095
#255 to 255
Two words
multiple of 4 in the
range #1020 to 1020
multiple of 4 in the
range #1020 to 1020
multiple of 4 in the
range #1020 to 1020
3.4.2.3 Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
bit[0] of the loaded value must be 1 for correct execution
a branch occurs to the address created by changing bit[0] of the loaded value to 0
if the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
3.4.2.4 Condition flags
These instructions do not change the flags.
3.4.2.5 Examples
LDR
R8, [R10]
; Loads R8 from the address in R10.
LDRNE
R2, [R5, #960]!
; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR
R2, [R9,#const#struc]
; const#struc is an expression evaluating
; to a constant in the range 0#4095.
STRH
R3, [R4], #4
; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD
R8, R9, [R3, #0x20]
; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
STRD
R0, R1, [R8], #-16
; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
3.4.3 LDR and STR, register offset
Load and Store with register offset.
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