參數(shù)資料
型號： EFM32TG822F32
廠商： Energy Micro
文件頁數(shù)： 23/136頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 標準包裝
其它名稱： 914-1031-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
119
www.energymicro.com
SIZE value
Region size
Value of N
1
Note
b01001 (9)
1KB
10
-
b10011 (19)
1MB
20
-
b11101 (29)
1GB
30
-
b11111 (31)
4GB
b01100
Maximum possible size
1In the RBAR, see Section 4.5.4 (p. 117) .
4.5.6 MPU access permission attributes
This section describes the MPU access permission attributes. The access permission bits, TEX, C, B,
S, AP, and XN, of the RASR, control access to the corresponding memory region. If an access is made
to an area of memory without the required permissions, then the MPU generates a permission fault.
Table 4.45 (p. 119) shows the encodings for the TEX, C, B, and S access permission bits.
Table 4.45. TEX, C, B, and S encoding
TEX
C
B
S
Memory type
Shareability
Other attributes
0
x
1
Strongly-ordered
Shareable
-
0
1
x
1
Device
Shareable
-
0
Not shareable
0
1
Normal
Shareable
Outer and inner write-through. No write allocate.
0
Not shareable
b000
1
Normal
Shareable
Outer and inner write-back. No write allocate.
0
Not shareable
0
1
Normal
Shareable
Outer and inner noncacheable.
0
1
x
1
Reserved encoding
-
0
x
1
Implementation defined attributes.
-
0
Not shareable
b001
1
Normal
Shareable
Outer and inner write-back. Write and read allocate.
0
x
1
Device
Not shareable
Nonshared Device.
0
1
x
1
Reserved encoding
-
b010
1
x
1
x
1
Reserved encoding
-
0
Not shareable
b1BB
A
1
Normal
Shareable
Cached memory
2, BB = outer policy, AA = inner policy.
1The MPU ignores the value of this bit.
2See Table 4.46 (p. 119) for the encoding of the AA and BB bits.
Table 4.46 (p. 119) shows the cache policy for memory attribute encodings with a TEX value is in
the range 4-7.
Table 4.46. Cache policy for memory attribute encoding
Encoding, AA or BB
Corresponding cache policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
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