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3Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status
of the exceptions, but see the Caution in this section.
If you disable a system handler and the corresponding fault occurs, the processor treats the fault as
a hard fault.
You can write to this register to change the pending or active status of system exceptions. An OS kernel
can write to the active bits to perform a context switch that changes the current exception type.
Caution
Software that changes the value of an active bit in this register without correct adjustment to
the stacked content can cause the processor to generate a fault exception. Ensure software that
writes to this register retains and subsequently restores the current active status.
After you have enabled the system handlers, if you have to change the value of a bit in this
register you must use a read-modify-write procedure to ensure that you change only the required
bit.
4.3.11 Configurable Fault Status Register
The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register
summary in Table 4.12 (p. 94) for its attributes. The bit assignments are:
Mem ory Managem ent
Fault St at us Regist er
31
16 15
8 7
0
Usage Fault St at us Regist er
Bus Fault St at us
Regist er
UFSR
BFSR
MMFSR
The following subsections describe the subregisters that make up the CFSR:
The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
access the complete CFSR with a word access to 0xE000ED28
access the MMFSR with a byte access to 0xE000ED28
access the MMFSR and BFSR with a halfword access to 0xE000ED28
access the BFSR with a byte access to 0xE000ED29
access the UFSR with a halfword access to 0xE000ED2A.
4.3.11.1 Memory Management Fault Status Register
The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are:
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