參數(shù)資料
型號(hào): EFM32TG210F32
廠商: Energy Micro
文件頁(yè)數(shù): 60/136頁(yè)
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 32-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1034-6
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
3
www.energymicro.com
Figure 1.1. EFM32 Cortex-M3 implementation
Processor
core
NVIC
Debug
Access
Port
Mem ory
prot ect ion unit
WIC
Serial
Wire
viewer
Bus m at rix
Code
int erface
SRAM and
peripheral int erface
Dat a
wat chpoint s
Flash
pat ch
EFM32 Cort ex-M3
processor
Em bedded Trace
Macrocell
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional
power efficiency through an efficient instruction set and extensively optimized design, providing high-
end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction
set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction
set provides the exceptional performance expected of a modern 32-bit architecture, with the high code
density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides
up to 8 interrupt priority levels. The tight integration of the processor core and NVIC provides fast
execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is
achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-
multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead
from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from
one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep
function that enables the entire device to be rapidly powered down.
1.2.1 System level interface
The Cortex-M3 processor provides multiple interfaces using AMBA technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data
handling.
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