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| 型號： | EFM32TG210F32 |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 62/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 32KB FLASH 32-QFN |
| 特色產(chǎn)品： | EFM32 Tiny Gecko |
| 標準包裝： | 1 |
| 系列： | Tiny Gecko |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 32MHz |
| 連通性： | EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x12b，D/A 1x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VQFN 裸露焊盤 |
| 包裝： | 標準包裝 |
| 其它名稱： | 914-1034-6 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
31
www.energymicro.com
if the register is 0 the processor stops executing instructions and enters sleep mode
if the register is 1 the processor clears the register to 0 and continues executing instructions without
entering sleep mode.
See Section 3.10.11 (p. 86) for more information.
If the event register is 1, this indicate that the processor must not enter sleep mode on execution
of a WFE instruction. Typically, this is because the processor has executed an SEV instruction, see
Section 3.10.9 (p. 85) . Software cannot access this register directly.
2.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an
exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism
in applications that only require the processor to run when an exception occurs.
2.5.2 Wakeup from sleep mode
The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode.
2.5.2.1 Wakeup from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause
exception entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and
before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK
bit to 0. If an interrupt arrives that is enabled and has a higher priority than current exception priority,
the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK
to zero. For more information about PRIMASK and FAULTMASK see Section 2.1.3.6 (p. 11) .
2.5.2.2 Wakeup from WFE
The processor wakes up if:
it detects an exception with sufficient priority to cause exception entry
in a multiprocessor system, another processor in the system executes an SEV instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and
wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception
entry. For more information about the SCR see Section 4.3.7 (p. 100) .
2.5.3 The Wakeup Interrupt Controller
The Wakeup Interrupt Controller (WIC) is a peripheral that can detect an interrupt and wake the
processor from deep sleep mode. The WIC is enabled only when the DEEPSLEEP bit in the SCR is
set to 1, see Section 4.3.7 (p. 100) .
The WIC is not programmable, and does not have any registers or user interface. It operates entirely
from hardware signals.
When the WIC is enabled and the processor enters deep sleep mode, the power management unit
in the system can power down most of the Cortex-M3 processor. This has the side effect of stopping
the SysTick timer. When the WIC receives an interrupt, it takes a number of clock cycles to wakeup
the processor and restore its state, before it can process the interrupt. This means interrupt latency is
increased in deep sleep mode.
Note
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