參數(shù)資料
型號: EFM32TG210F32
廠商: Energy Micro
文件頁數(shù): 58/136頁
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 32-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1034-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
28
www.energymicro.com
this value provide information on the return stack and processor mode. Table 2.16 (p. 28) shows the
EXC_RETURN[3:0] values with a description of the exception return behavior.
The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into the PC
it indicates to the processor that the exception is complete, and the processor initiates the exception
return sequence.
Table 2.16. Exception return behavior
EXC_RETURN[3:0]
Description
bXXX0
Reserved.
b0001
Return to Handler mode.
Exception return gets state from MSP.
Execution uses MSP after return.
b0011
Reserved.
b01X1
Reserved.
b1001
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
b1101
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
b1X11
Reserved.
2.4 Fault handling
Faults are a subset of the exceptions, see Section 2.3 (p. 22) . The following generate a fault:
a bus error on:
an instruction fetch or vector table load
a data access
an internally-detected error such as an undefined instruction or an attempt to change state with a BX
instruction
attempting to execute an instruction from a memory region marked as Non-Executable (XN)
an MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.4.1 Fault types
Table 2.17 (p. 28) shows the types of fault, the handler used for the fault, the corresponding fault
status register, and the register bit that indicates that the fault has occurred. See Section 4.3.11 (p.
105) for more information about the fault status registers.
Table 2.17. Faults
Fault
Handler
Bit name
Fault status register
Bus error on a vector read
VECTTBL
Fault escalated to a hard fault
Hard fault
FORCED
MPU mismatch:
-
on instruction access
IACCVIOL
1
on data access
Memory
management
fault
DACCVIOL
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