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參數(shù)資料
| 型號： | EDX5116ABSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 512M比特XDR DRAM內(nèi)存（32M的話？16位） |
| 文件頁數(shù)： | 64/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
64
EDX5116ABSE
Receive/Transmit Timing
Clocking
Figure 48 shows a timing diagram for the CFM/CFMN clock
pins of the memory component. This diagram represents a
magnified view of these pins. This diagram shows only one
clock cycle.
CFM and CFMN are differential signals: one signal is the com-
plement of the other. They are also high-true signals — a low
voltage represents a logical zero and a high voltage represents a
logical one. There are two crossing points in each clock cycle.
The primary crossing point includes the high-voltage-to-low-
voltage transition of CFM (indicated with the arrowhead in the
diagram). The secondary crossing point includes the low-volt-
age-to-high-voltage transition of CFM. All timing events on
the RSL signals are referenced to the first set of edges.
Timing events are measured to and from the crossing point of
the CFM and CFMN signals. In the timing diagram, this is how
the clock-cycle time (t
CYCLE
or t
CYC,CFM
), clock-low time
(t
L,CFM
) and clock-high time (t
H,CFM
) are measured.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise
(t
R,CFM
) and fall time (t
F,CFM
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
IL,CFM
+ 0.2*(V
IH,CFM
-V
IL,CFM
)
80% = V
IL,CFM
+ 0.8*(V
IH,CFM
-V
IL,CFM
)
Figure 48
Clocking Waveforms
CFM
CFMN
t
CYCLE
or t
CYC,CFM
t
R,CFM
80%
20%
V
IL,CFM
logic 0
V
IH,CFM
logic 1
t
L,CFM
t
H,CFM
t
F,CFM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-3C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-2A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
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