參數(shù)資料
型號(hào)： EDX5116ABSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 512M比特XDR DRAM內(nèi)存（32M的話？16位）
文件頁(yè)數(shù)： 22/78頁(yè)
文件大?。?/td> 3611K
代理商： EDX5116ABSE
Preliminary Data Sheet E0643E30 (Ver. 3.0)
22
EDX5116ABSE
Memory Operations
Write Transactions
Figure 9 shows four examples of memory write transactions. A
transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of
the memory core and the address of the memory access deter-
mine how many request packets are needed to perform the
access.
The first timing diagram shows a page-hit write transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, write data may be directly written into the sense
amp array for the bank, and row operations (activate or pre-
charge) are not needed. A COL packet with WR command to
column Ca1 of bank Ba is presented on edge T
0
, and a second
COL packet with WR command to column Ca1 of bank Ba is
presented on edge T
2
. Two write data packets D(a1) and D(a2)
follow these COL packets after the write data delay t
CWD
. The
two COL packets are separated by the column-cycle time t
CC
.
This is also the length of each write data packet.
The second timing diagram shows an example of a page-miss
write transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to close the
present row (precharge) and access the requested row (acti-
vate). A precharge command (PRE to bank Ba) is presented on
edge T
0
. An activate command (ACT to row Ra of bank Ba) is
presented on edge T
6
a time t
RP
later. A COL packet with WR
command to column Ca1 of bank Ba is presented on edge T
7
a
time t
RCD-W
later. A second COL packet with WR command
to column Ca2 of bank Ba is presented on edge T
9
. Two write
data packets D(a1) and D(a2) follow these COL packets after
the write data delay t
CWD
. The two COL packets are separated
by the column-cycle time t
CC
. This is also the length of each
write data packet.
The third timing diagram shows an example of a page-empty
write transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to access the
requested row (activate). An activate command (ACT to row
Ra of bank Ba) is presented on edge T
0
. A COL packet with
WR command to column Ca1 of bank Ba is presented on edge
T
1
a time t
RCD-W
later. A second COL packet with WR com-
mand to column Ca2 of bank Ba is presented on edge T
3
. Two
write data packets D(a1) and D(a2) follow these COL packets
after the write data delay t
CWD
. The two COL packets are sepa-
rated by the column-cycle time t
CC
. This is also the length of
each write data packet. After the final write command, it may
be necessary to close the present row (precharge). A precharge
command (PRE to bank Ba) is presented on edge T
14
a time
t
WRP
after the last COL packet with a WR command. The
decision whether to close the bank or leave it open is made by
the memory controller and its page policy.
The fourth timing diagram shows another example of a page-
empty write transaction. This is similar to the previous example
except that only a single write command is presented, rather
than two write commands. This example shows that even with
a minimum length write transaction, the t
RAS
parameter will
not be a constraint. The t
RAS
measures the minimum time
between an activate command and a precharge command to a
bank. This time interval is also constrained by the sum t
RCD-
W
+t
WRP
which will be larger for a write transaction. These two
constraints ( t
RAS
and t
RCD-W
+t
WRP
) will be a function of the
memory device’s speed bin and the data transfer length (the
number of write commands issued between the activate and
precharge commands), and the t
RAS
parameter could become a
constraint for write transactions for future speed bins. In this
example, the sum t
RCD-W
+t
WRP
is greater than t
RAS
by the
amount
t
RAS
.
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