參數(shù)資料
型號(hào)： EDX5116ABSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 512M比特XDR DRAM內(nèi)存（32M的話？16位）
文件頁(yè)數(shù)： 56/78頁(yè)
文件大?。?/td> 3611K
代理商： EDX5116ABSE
Preliminary Data Sheet E0643E30 (Ver. 3.0)
56
EDX5116ABSE
Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW. This feature is simultaneous activation, and the timing
of several cases is shown in Figure 46.
The t
RR
parameter specifies the minimum spacing between
packets with activation commands in XDR DRAMs with a sin-
gle bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The t
RR-D
parameter specifies
the minimum spacing between packets with activation com-
mands to different bank sets in a XDR DRAM with multiple
bank sets.
In Figure 46, Case 4 shows an example when both t
RR
and t
RR-
D
must be at least 4*t
CYCLE
. In such a case, activation com-
mands to different bank sets satisfy the same constraint as acti-
vation commands to the same bank set.
In Figure 46, Case 2 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 2*t
CYCLE
. In such a
case, an activation command to one bank set may be inserted
between two activation commands to a different bank set.
In Figure 46, Case 1 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 1*t
CYCLE
. As in the
previous case, an activation command to one bank set may be
inserted between two activation commands to a different bank
set. In this case, the middle activation command will not be
symmetrically placed relative to the two outer activation com-
mands.
In Figure 46, Case 0 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 0*t
CYCLE
. This
means that two activation commands may be issued on the
same CFM clock edge. This is only possible by using the delay
mechanism in one of the two commands. See “Dynamic
Request Scheduling” on page 20. In the example shown, the
packet with the REFA command is received one cycle before
the command with the ACT command, and the REFA com-
mand includes a one cycle delay. Both activation commands
will be issued internally to different bank sets on the same
CFM clock edge.
Figure 46
S imultaneous Activation
—
t
RR-D
Cases
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
RR-D
ACT
REFA
ACT
t
RR-D
Case 4: t
RR-D
= 4*t
CYCLE
REFA & ACT have same t
RR
t
RR
ACT
REFA
ACT
Case 2: t
RR-D
= 2*t
CYCLE
REFA fits between two ACT
t
RR-D
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Case 1: t
RR-D
= 1*t
CYCLE
REFA fits between two ACT
t
RR
ACT
REFA
ACT
Case 0: t
RR-D
= 0*t
CYCLE
REFA simultaneous with ACT
(REFA uses delay=1*t
CYCLE
)
t
RR-D
t
RR
ACT
REFA
ACT
t
RR-D
set different from two ACT
note - REFA is directed to bank
set different from two ACT
note - REFA is directed to bank
set different from ACT at T
12
note - REFA is directed to bank
a
a
a
a) EDX5116ABSE does not support these cases.
The minimum value of t
RR-D
is 4.
相關(guān)PDF資料
PDF描述
EDX5116ABSE-3C-E 512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-4C-E 512M bits XDR DRAM (32M words ?16 bits)
EDX5116ADSE 512M bits XDR⑩ DRAM
EDX5116ADSE-3B-E 512M bits XDR⑩ DRAM
EDX5116ADSE-3C-E 512M bits XDR⑩ DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDX5116ABSE-2A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-3A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-3B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-3C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-4C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
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