- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384283 > EDX5116ABSE (Elpida Memory, Inc.) 512M bits XDR DRAM (32M words ?16 bits) PDF資料下載
參數(shù)資料
| 型號(hào)： | EDX5116ABSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 512M比特XDR DRAM內(nèi)存（32M的話？16位） |
| 文件頁數(shù)： | 63/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當(dāng)前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Preliminary Data Sheet E0643E30 (Ver. 3.0)
63
EDX5116ABSE
t
RCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD
read command to the same bank.
5
7
7
t
CYCLE
Figure 4 -
Figure 7
t
RCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-
WR or COL-WRM write command to the same bank.
1
3
3
t
CYCLE
Figure 4 -
Figure 7
t
CAC
Column access delay: interval from COL-RD read command to Q read data
6
7
7
t
CYCLE
Figure 10
t
CWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write
data.
3
3
3
t
CYCLE
Figure 9
t
CC
Column-to-column time: interval between successive COL-RD commands, or between succes-
sive COL-WR or COLM-WRM commands.
2
2
2
t
CYCLE
Figure 4 -
Figure 7
t
RW-BUB,
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D
write data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
t
CYCLE
Figure 13
t
WR-BUB,
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read
data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
t
CYCLE
Figure 13
t
RW
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-
WRM write command.
d
8
9
9
t
CYCLE
Figure 12
t
WR
Write-to-read time: interval between a COL-WR or t
WR
COLM-WRM write command and a COL-RD read command. t
WR-De
9
2
10
2
10
2
t
CYCLE
Figure 12
t
RDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE pre-
charge command to the same bank.
3
4
4
t
CYCLE
Figure 4 -
Figure 7
t
WRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a
ROWP-PRE precharge command to the same bank.
10
12
12
t
CYCLE
Figure 4 -
Figure 7
t
DR
Write data-to-read time: interval between the start of D write data and a COL-RD read com-
mand to the same bank.
6
7
7
t
CYCLE
Figure 12
t
DP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge com-
mand to the same bank.
7
9
9
t
CYCLE
Figure 9
t
LRRn-LRRn
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command.
f
16
20
24
t
CYCLE
Table 4
t
REFx-LRRn
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
16
20
24
t
CYCLE
Table 4
t
LRRn-REFx
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
16
20
24
t
CYCLE
Table 4
a. The t
RC,MIN
parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon how many
column accesses (each requiring t
CC
) are performed in each row access (t
RC
). The table lists the special cases (t
RC-R, 2tCC
, t
RC-W 2tCC, noERAW
, t
RC-W 2tCC, ERAW
) in which two col-
umn accesses are performed in each row access. Note that t
RC-W 2tCC, ERAW
uses a relaxed value of t
RCD-W
that is equal to t
RCD-R,MIN
.
All other parameters are minimum.
b. t
PP-D
is the t
PP
parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 57.
c. t
RR-D
is the t
RR
parameter for activates to different bank sets. See “Simultaneous Activation” on page 56.
d. See “Propagation Delay” on page 28.
e. t
WR-D
is the t
WR
parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 54. Also, note that the value of t
WR-D
may
not take on the values {3,5,7} within the range{t
WR-D,MIN
, ... t
WR,MIN
-1}. t
WR-D
may assume any value
≥
t
WR,MIN
.
f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,ROWP-LRR2}
ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,ROWP-REFP}
Table 17
Timing Parameters (Continued)
Symbol
Parameter and Other Conditions
Min
(A)
Min
(B)
Min
(C)
Units
Figure(s)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-3C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-2A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。