參數(shù)資料
型號(hào): EDX5116ABSE-3B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits XDR DRAM (32M words ?16 bits)
中文描述: 32M X 16 RAMBUS, PBGA104
封裝: LEAD FREE, FBGA-104
文件頁(yè)數(shù): 9/78頁(yè)
文件大?。?/td> 3611K
代理商: EDX5116ABSE-3B-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
9
EDX5116ABSE
Figure 2
512Mb (8x4Mx16) X DR DRAM Block Diagram
1
1:2 Demux
Decode
12
RQ11..0
1:16 Demux
16:1 Mux
16/t
CC
2/t
CYCLE
reg
12
12
CFMCFMN
1/t
CYCLE
2/t
CYCLE
16/ t
CC
1/t
CYCLE
12
12
4
RST,SCK,CMD,SDI
Control Registers
1
SDO
16x16*2
6
*2
12
ACT delay
{0..1}*t
CYCLE
1/t
RR
ACT logic
.
.
d
Bank 0
1
ACT
ACT
ROW
1
1/t
PP
.
d
1
PRE
PRE
PRE delay
{0..3}*t
CYCLE
PRE logic
ROW
.
Sense Amp 0
.
1
r
1/t
CC
.
d
1
R/W
R/W
COL
COL
RD,WR
delay
COL logic
.
.
7
BA,BR,REFBr
R,REFr
BP,BR,REFB r
BC
C
SC
M
.
Bank Array
Sense Amp Array
16x16*2
6
8
.
.
.
.
Dynamic Width Demux (WR)
16x16
r
termination
VTERM
2
1
VREF
REFB,REFr
WIDTH
{0..1}*t
CYCLE
DQ15..0
DQN15..0
16
16
16
16
16/t
CC
16x16*2
6
16x16
16x16
16x16
4
3
3
3
3
3
6+4
12
(2
3
- 1)
Bank
(2
3
- 1)
Sense Amp
2
3
2
3
3
6
16x16*2
6
12
2
3
16
D[15:0][15:0]
S[15:0][15:0]
16
16x16
16x16
WIDTH
Q[15:0][15:0]
Dynamic Width Mux (RD)
Byte Mask (WR)
Power Mode Logic
Calibration Logic
Refresh Logic
Initialization Logic
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