參數(shù)資料
型號: EDX5116ABSE-3B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits XDR DRAM (32M words ?16 bits)
中文描述: 32M X 16 RAMBUS, PBGA104
封裝: LEAD FREE, FBGA-104
文件頁數(shù): 70/78頁
文件大小: 3611K
代理商: EDX5116ABSE-3B-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
70
EDX5116ABSE
Serial Interface Receive Timing
Figure 52 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magni-
fied view of the pins only a few clock cycles.
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the V
REF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(t
R,SCK
and t
IR,SI
) and fall time (t
F,SCK
and t
IF,SI
) of the signals
are measured from the 20% and 80% points of the full-swing
levels.
20% = V
IL,SI
+ 0.2*(V
IH,SI
-V
IL,SI
)
50% = V
IL,SI
+ 0.5*(V
IH,SI
-V
IL,SI
)
80% = V
IL,SI
+ 0.8*(V
IH,SI
-V
IL,SI
)
There is one receiving window defined for each serial interface
signal (RST,CMD and SDI pins). This window has a set time
(t
S,RQ
) and a hold time (t
H,RQ
) measured around the falling
edge of the SCK clock signal.
Figure 52
S erial Interfac e Rec eive Waveforms
SCK
t
CYC,SCK
80%
20%
V
IL,SI
logic 1
t
IR,
SI
V
IH,SI
logic 0
V
REF,RSL
t
S,
SI
t
H,
SI
t
IF,
SI
80%
20%
V
IL,SI
logic 1
V
IH,SI
logic 0
V
REF,RSL
t
L,SCK
t
H,SCK
t
F,SCK
t
R,SCK
RST
CMD
SDI
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