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| 型號： | EDX5116ABSE-3B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 26/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-3B-E |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
26
EDX5116ABSE
Interleaved Transactions
Figure 11 shows two examples of interleaved transactions.
Interleaved transactions are overlapped with one another; a
transaction is started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved
write transactions. Each transaction assumes a page-empty
access; that is, a bank is in a closed state prior to an access, and
is precharged after the access. With this assumption, each
transaction requires the same number of request packets at the
same relative positions. If banks were allowed to be in an open
state, then each transaction would require a different number
of request packets depending upon whether the transaction
was page-empty, page-hit, or page-miss. This situation is more
complicated for the memory controller, and will not be ana-
lyzed in this document.
In the interleaved page-empty write example, there are four
sets of request pins RQ11..0 shown along the left side of the
timing diagram. The first three show the timing slots used by
each of the three request packet types (ACT, COL, and PRE),
and the fourth set (ALL) shows the previous three merged
together. This allows the pattern used for allocating request
slots for the different packets to be seen more clearly.
The slots at {T
0
, T
4
, T
8
, T
12
, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the t
RR
parameter. There should not be interference between the inter-
leaved transactions due to resource conflicts because each bank
address — Ba, Bb, Bc, Bd, and Be — is assumed to be differ-
ent from another. If two of the bank addresses are the same,
the later transaction would need to wait until the earlier trans-
action had completed its precharge operation. Five different
banks are needed because the effective t
RC
(t
RC
+
t
RC
) is
20*t
CYCLE
.
The slots at {T
1
, T
3
, T
5
, T
7
, T
9
, T
11
, ...} are used for COL
packets with WR commands. This frequency of the COL
packet spacing is determined by the t
CC
parameter and by the
fact that there are two column accesses per row access. The
phasing of the COL packet spacing is determined by the t
RCD-
W
parameter. If the value of t
RCD-W
required the COL packets
to occupy the same request slots as the ROWA packets (this
case is not shown), the DELC field in the COL packet could
be used to place the COL packet one t
CYCLE
earlier.
The DQ bus slots at {T
7
, T
9
, T
11
, T
13
, ...} carry the write data
packets {D(a1), D(a2), D(b1), D(b2), ....}. Two write data pack-
ets are written to a bank in each transaction. The DQ bus is
completely filled with write data; no idle cycles need to be
introduced because there are no resource conflicts in this
example.
The slots at {T
14
, T
18
, T
22
, ...} are used for ROWP packets
with PRE commands. This frequency of ROWP packet spac-
ing is determined by the t
PP
parameter. The phasing of the
ROWP packet spacing is determined by the t
WRP
parameter. If
the value of t
WRP
required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
t
CYCLE
There is an example of an interleaved page-empty read at the
bottom of the figure. As before, there are four sets of request
pins RQ11..0 shown along the left side of the timing diagram,
allowing the pattern used for allocating request slots for the
different packets to be seen more clearly.
The slots at {T
0
, T
4
, T
8
, T
12
, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the t
RR
parameter. There should not be interference between the inter-
leaved transactions due to resource conflicts because each bank
address — Ba, Bb, Bc, and Bd — is assumed to be different
from another. Four different banks are needed because the
effective t
RC
is 16*t
CYCLE
.
The slots at {T
5
, T
7
, T
9
, T
11
, ...} are used for COL packets
with RD commands. This frequency of the COL packet spac-
ing is determined by the t
CC
parameter and by the fact that
there are two column accesses per row access. The phasing of
the COL packet spacing is determined by the t
RCD-R
parame-
ter. If the value of t
RCD-R
required the COL packets to occupy
the same request slots as the ROWA packets (this case is not
shown), the DELC field in the COL packet could be used to
place the packet one t
CYCLE
earlier.
The DQ bus slots at {T
11
, T
13
, T
15
, T
17
, ...} carry the read data
packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}. Two read data pack-
ets are read from a bank in each transaction. The DQ bus is
completely filled with read data — that is, no idle cycles need
to be introduced because there are no resource conflicts in this
example.
The slots at {T
10
, T
14
, T
18
, T
22
, ...} are used for ROWP pack-
ets with PRE commands. This frequency of the ROWP packet
spacing is determined by the t
PP
parameter. The phasing of the
ROWP packet spacing is determined by the t
RDP
parameter. If
the value of t
RDP
required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
t
CYCLE
s earlier.
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|---|---|
| EDX5116ABSE-2A-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3A-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-3C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
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