參數(shù)資料
型號(hào): EDS2532AABJ-6B
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM (8M words ?32 bits)
中文描述: 256M位的SDRAM(800萬(wàn)字?32位)
文件頁(yè)數(shù): 8/48頁(yè)
文件大?。?/td> 614K
代理商: EDS2532AABJ-6B
EDS2532AABJ-6B
Data Sheet E0509E30 (Ver. 3.0)
8
Test Conditions
Input and output timing reference levels: 1.4V
Input waveform and output load: See following figures
tT
2.4 V
0.4 V0.8 V
2.0 V
input
t
T
I/O
CL
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-6B
Frequency (MHz)
166
tCK (ns)
Symbol
6
Unit
Notes
Active command to column command (same bank)
l
RCD
3
tCK
1
Active command to active command (same bank)
l
RC
10
tCK
1
Active command to precharge command (same bank)
l
RAS
7
tCK
1
Precharge command to active command (same bank)
l
RP
3
tCK
1
Write recovery or data-in to precharge command (same bank)
l
DPL
2
tCK
1
Active command to active command (different bank)
l
RRD
2
tCK
1
Self refresh exit time
l
SREX
1
2
Last data in to active command (Auto precharge, same bank)
l
DAL
5
tCK
= [
l
DPL +
l
RP]
Self refresh exit to command input
l
SEC
10
tCK
= [
l
RC]
3
Precharge command to high impedance
(CL = 2)
l
HZP
tCK
(CL = 3)
l
HZP
3
tCK
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
l
APR
1
tCK
l
EP
tCK
(CL = 3)
l
EP
–2
tCK
Column command to column command
l
CCD
1
tCK
Write command to data in latency
l
WCD
0
tCK
DQM to data in
l
DID
0
tCK
DQM to data out
l
DOD
2
tCK
CKE to CLK disable
l
CLE
1
tCK
Register set to active command
l
MRD
2
tCK
/CS to command disable
l
CDD
0
tCK
Power down exit to command input
l
PEC
1
tCK
Notes: 1.
l
RCD to
l
RRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
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