參數(shù)資料
型號(hào): EDS2532AABJ-6B
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM (8M words ?32 bits)
中文描述: 256M位的SDRAM(800萬(wàn)字?32位)
文件頁(yè)數(shù): 16/48頁(yè)
文件大小: 614K
代理商: EDS2532AABJ-6B
EDS2532AABJ-6B
Data Sheet E0509E30 (Ver. 3.0)
16
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
4
L
L
H
H
BA, RA
ACT
Bank and row active*
9
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh*
9
Remark: H: VIH. L: VIL.
×
: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if
l
MRD is not satisfied.
L
L
L
L
MODE
MRS
Mode register set*
8
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