參數(shù)資料
型號: EDS2516CDTA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits SDRAM (16M words x 16 bits)
中文描述: 16M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù): 9/50頁
文件大?。?/td> 703K
代理商: EDS2516CDTA-75-E
EDS2516CDTA
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
9
Relationship Between Frequency and Minimum Latency
Frequency (MHz)
133
100
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command (same
bank)
Precharge command to activecommand (same
bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Symbol
7.5
10
Unit
Notes
l
RCD
3
2
tCK
1
l
RC
9
7
tCK
1
l
RAS
6
5
tCK
1
l
RP
3
2
tCK
1
l
DPL
2
2
tCK
1
l
RRD
2
2
tCK
1
Self refresh exit time
l
SREX
1
1
tCK
2
Last data in to active command
(Auto precharge, same bank)
l
DAL
5
4
tCK
= [
l
DPL +
l
RP]
Self refresh exit to command input
l
SEC
9
7
tCK
= [
l
RC]
3
Precharge command to high impedance
(CL = 2)
l
HZP
2
tCK
(CL = 3)
l
HZP
3
tCK
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
l
APR
1
1
tCK
l
EP
–1
tCK
(CL = 3)
l
EP
–2
–2
tCK
Column command to column command
l
CCD
1
1
tCK
Write command to data in latency
l
WCD
0
0
tCK
DQM to data in
l
DID
0
0
tCK
DQM to data out
l
DOD
2
2
tCK
CKE to CLK disable
l
CLE
1
1
tCK
Register set to active command
l
MRD
2
2
tCK
/CS to command disable
l
CDD
0
0
tCK
Power down exit to command input
l
PEC
1
1
tCK
Notes: 1.
l
RCD to
l
RRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
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