參數(shù)資料
型號: EDS2516CDTA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits SDRAM (16M words x 16 bits)
中文描述: 16M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù): 36/50頁
文件大小: 703K
代理商: EDS2516CDTA-75-E
EDS2516CDTA
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
36
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by
l
HZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by
l
EP must be assured as
an interval from the final data output to precharge command execution.
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
l
EP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=3
l
EP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
High-Z
l
HZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
DQ
READ
PRE/PALL
out A0
l
HZP =3
High-Z
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
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