參數(shù)資料
型號(hào)： EDL1216CASA
廠商： Elpida Memory, Inc.
英文描述： 128M bits Mobile RAM
中文描述： 128M的內(nèi)存位移動(dòng)
文件頁(yè)數(shù)： 25/59頁(yè)
文件大?。?/td> 479K
代理商： EDL1216CASA
EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
25
Operation of the Mobile RAM
Precharge
The precharge command can be issued anytime after tRAS
min. is satisfied. Soon after the precharge command is
issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The
parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge
command can be issued without losing any data in the burst is as follows.
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=4
READ
READ
Q1
Q2
Q3
Q4
PRE
Hi-Z
Q1
Q2
Q3
Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
/CAS latency = 2
DQ
Command
/CAS latency = 3
DQ
T8
Precharge
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL
(min.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (min.) with clock cycle time. In summary, the precharge command can be issued relative
to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the
reference; plus means time after the reference.
/CAS latency
Read
Write
2
3
-1
-2
+tDPL(min.)
+tDPL(min.)
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