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參數(shù)資料
| 型號： | EDL1216AASA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | GT 3C 3#12 SKT RECP |
| 中文描述： | 128M的內(nèi)存位移動 |
| 文件頁數(shù)： | 9/59頁 |
| 文件大小： | 479K |
| 代理商： | EDL1216AASA |
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EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
9
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Mobile RAM suspends operation.
When the Mobile RAM is not in burst mode and CKE is negated, the device enters power down mode. During power
down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. It does not
depend on the bit organization.
Column Address is determined by A0 to 8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank A
L
L
Bank B
H
L
Bank C
L
H
Bank D
Remark: H: VIH. L: VIL.
×
: VIH or VIL
UDQM and LDQM
(input pins)
UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the
output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the
memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero.
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
H
H
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDL1216AASA-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
| EDL1216AASA-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits Mobile RAM |
| EDL1216BASA-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
| EDL1216CASA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits Mobile RAM |
| EDL1216CASA-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
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