參數(shù)資料
型號(hào): EDE5104GBSA-5A-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: RxxPxx Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 3.3V; Power: 1W; EN 60950 certified, rated for 250VAC; UL-60950-1 / CSA C22.2 certified; 5.2kVDC Isolation for 1 Minute; Optional Continuous Short Circuit Protected; 2 Chamber Transformer System; UL94V-0 Package Material; Efficiency to 80%
中文描述: 128M X 4 DDR DRAM, 0.5 ns, PBGA64
封裝: MICRO, BGA-64
文件頁(yè)數(shù): 24/66頁(yè)
文件大?。?/td> 697K
代理商: EDE5104GBSA-5A-E
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
24
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Note
Extended Mode
H
×
×
×
×
DESL
Nop -> Enter idle after tMRD
register accessing L
H
H
H
×
NOP
Nop -> Enter idle after tMRD
L
H
L
H
BA, CA, A10 (AP)
READ
ILLEGAL
L
H
L
H
BA, CA, A10 (AP)
READA
ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRIT
ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10 (AP)
PRE
ILLEGAL
L
L
H
L
A10 (AP)
PALL
ILLEGAL
L
L
L
H
×
REF
ILLEGAL
L
L
L
H
×
SELF
ILLEGAL
L
L
L
L
BA, MRS-OPCODE
MRS
ILLEGAL
Remark: H = VIH. L = VIL.
×
= VIH or VIL
Notes: 1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.
L
L
L
L
BA, EMRS-OPCODE
EMRS
ILLEGAL
相關(guān)PDF資料
PDF描述
EDE5108GBSA-5A-E INNOLINE: Rxx-100_150A - Compact High Voltage Power Supplies - 5 Watt in Low Profile DIP24 Package - 3000VDC Isolation - Remote Voltage Programming by External Voltage or Resistance - Continuous Short Circuit Protection - Cascadeable to generate Output Voltages of up to 420VDC
EDE5104GBSA 512M bits DDR-II SDRAM
EDE5108ABSE 512M bits DDR2 SDRAM
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