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參數(shù)資料
| 型號： | EDE5104AESK-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.6 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 37/66頁 |
| 文件大小： | 697K |
| 代理商： | EDE5104AESK-4A-E |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
37
Bank Activate Command [ACT]
The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the
clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A13 is
used to determine which row to activate in the selected bank. The Bank activate command must be applied before
any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can
accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not
satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the
R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.)
is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be
precharged before another bank activate command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank
activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to
tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is
determined by (tRRD).
/CK
CK
Address
Command
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
tRCD(min.)
tRAS
tRP
tRC
ROW: 0
ACT
Bank0
Active
Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)
Bank1
Active
Bank0
Active
Bank0
Precharge
Bank1
Precharge
Posted
READ
Posted
READ
ACT
PRE
PRE
ACT
COL: 0
ROW: 0
ROW: 1
COL: 1
tRCD =1
tCCD
Additive latency (AL)
tRRD
Bank0 Read begins
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|---|---|
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
| EDE5104AJSE | EDE5104AJSE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE_1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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