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參數(shù)資料
| 型號： | EDE5104AESK-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.6 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5104AESK-4A-E |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
18
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol
Previous
cycle
Current
cycle
/CS
/RAS
/CAS
/WE
BA1,
BA0
A13 to
A11
A10
A0 to
A9
Notes
Mode register set
MRS
H
H
L
L
L
L
BA0 = 0 and MRS OP Code
1
Extended mode register set
EMRS
H
H
L
L
L
L
BA0 = 1 and EMRS OP Code
1
Auto refresh
REF
H
H
L
L
L
H
×
×
×
×
1
Self refresh entry
SELF
H
L
L
L
L
H
×
×
×
×
1
Self refresh exit
SELFX
L
H
H
×
×
×
×
×
×
×
1, 6
L
H
L
H
H
H
×
×
×
×
Single bank precharge
PRE
H
H
L
L
H
L
BA
×
L
×
1, 2
Precharge all banks
PALL
H
H
L
L
H
L
×
×
H
×
1
Bank activate
ACT
H
H
L
L
H
H
BA
Row Address
1, 2
Write
WRIT
H
H
L
H
L
L
BA
Column L
Column 1, 2, 3
Write with auto precharge
WRITA
H
H
L
H
L
L
BA
Column H
Column 1, 2, 3
Read
READ
H
H
L
H
L
H
BA
Column L
Column 1, 2, 3
Read with auto precharge
READA H
H
L
H
L
H
BA
Column H
Column 1, 2, 3
No operation
NOP
H
×
L
H
H
H
×
×
×
×
1
Device deselect
DESL
H
×
H
×
×
×
×
×
×
×
1
Power down mode entry
PDEN
H
L
H
×
×
×
×
×
×
×
1, 4
H
L
L
H
H
H
×
×
×
×
Power down mode exit
PDEX
L
H
H
×
×
×
×
×
×
×
1, 4
Remark: H = VIH. L = VIL.
×
= VIH or VIL
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as
″
Reads interrupted by a Read
″
in
burst read command [READ] or
″
Writes interrupted by a Write
″
in burst write command [WRIT].
4. The power down mode does not perform any refresh operations. The duration of power down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self refresh exit is asynchronous.
L
H
L
H
H
H
×
×
×
×
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
| EDE5104AJSE | EDE5104AJSE |
| EDE5108AJBG | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE_1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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