- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384280 > EDE5104AESK-4A-E (ELPIDA MEMORY INC) 512M bits DDR2 SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDE5104AESK-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.6 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5104AESK-4A-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
19
CKE Truth Table
CKE
Command(n)
*3
/CS, /RAS, /CAS, /WE
Current state*
2
Previous
cycle (n-1)*
1
Current
cycle (n)
*1
Operation (n)
*3
Notes
Power down
L
L
×
Maintain power down
11, 13, 15
L
H
DESL or NOP
Power down exit
4, 8, 11, 13
Self refresh
L
L
×
Maintain self refresh
11, 15
L
H
DESL or NOP
Self refresh exit
4, 5, 9
Bank Active
H
L
DESL or NOP
Active power down entry
4, 8, 10, 11, 13
All banks idle
H
L
DESL or NOP
Precharge power down entry
4, 8, 10, 11, 13
Any state other than
listed above
Remark: H = VIH. L = VIL.
×
= Don’t care
Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n
1) was the state of CKE at the previous clock
edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this
document.
5. On self refresh exit, [DESL] or [NOP] commands must be issued on every clock edge occurring during the
tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
6. Self refresh mode can only be entered from the all banks idle state.
7. Must be a legal command as defined in the command truth table.
8. Valid commands for power down entry and exit are [NOP] and [DESL] only.
9. Valid commands for self refresh exit are [NOP] and [DESL] only.
10. Power down and self-refresh can not be entered while read or write operations, (extended) mode register
set operations or precharge operations are in progress. See section Power Down and Self Refresh
Command for a detailed list of restrictions.
11. Minimum CKE high time is 3 clocks; minimum CKE low time is 3 clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh. See section ODT (On Die Termination).
13. The power down does not perform any refresh operations. The duration of power down mode is therefore
limited by the refresh requirements outlined in section automatic refresh command.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode.
15.
“
×
” means “don’t care” (including floating around VREF) in self refresh and power down. However ODT
must be driven high or low in power down if the ODT function is enabled (bit A2 or A6 set to “1” in
EMRS(1) ).
H
L
SELF
Self refresh entry
6, 9, 11, 13
H
H
Refer to the Command Truth Table
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
| EDE5104AJSE | EDE5104AJSE |
| EDE5108AJBG | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE_1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。