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參數(shù)資料
| 型號(hào)： | EDE5104AESK-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.6 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 16/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5104AESK-4A-E |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
16
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A13 (input pins)
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the respective bank. The address inputs also provide
the op-code during mode register set commands.
[Address Pins Table]
Address (A0 to A13)
Part number
Row address
Column address
Note
EDE5104ABSE
AX0 to AX13
AY0 to AY9, AY11
EDE5108ABSE
AX0 to AX13
AY0 to AY9
EDE5116ABSE
Note: 1. A13 pin is NC for
×
16 organization.
A10 (AP) (input pin)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1.
BA0, BA1 (input pins)
BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also
determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
AX0 to AX12
AY0 to AY9
1
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-
refresh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
| EDE5104AJSE | EDE5104AJSE |
| EDE5108AJBG | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE_1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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