參數(shù)資料
型號(hào): EDD1232ABBH
廠商: Elpida Memory, Inc.
英文描述: 128M bits DDR SDRAM
中文描述: 128兆位DDR SDRAM內(nèi)存
文件頁數(shù): 20/51頁
文件大?。?/td> 518K
代理商: EDD1232ABBH
EDD1232ABBH
Data Sheet E0874E40 (Ver. 4.0)
20
Auto-refresh command [REF]
This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The average refresh cycle is 7.8
μ
s. The output buffer becomes High-Z after auto-
refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can
be issued tRFC
after the last auto-refresh command.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not
disable DLL.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.
To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After
the exit, input auto-refresh command within 7.8
μ
s.
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX after the cycle when [PDEX] is issued.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD1232ABBH-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1232ACBH 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
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