參數(shù)資料
型號: EDD1232ABBH
廠商: Elpida Memory, Inc.
英文描述: 128M bits DDR SDRAM
中文描述: 128兆位DDR SDRAM內(nèi)存
文件頁數(shù): 1/51頁
文件大?。?/td> 518K
代理商: EDD1232ABBH
Document No. E0874E40 (Ver. 4.0)
Date Published April 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007
DATA SHEET
128M bits DDR SDRAM
EDD1232ABBH (4M words
×
32 bits)
Specifications
Density: 128M bits
Organization
1M words
×
32 bits
×
4 banks
Package: 144-ball FBGA
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
2.5V
±
0.125V
Data rate: 400Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 3
Precharge: auto precharge operation for each burst
access
Driver strength: weak/matched
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/32ms
Average refresh period: 7.8
μ
s
Operating ambient temperature range
TA = 0
°
C to +70
°
C
Features
×
32 organization
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD1232ABBH-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
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