參數(shù)資料
型號: EDD1232ABBH
廠商: Elpida Memory, Inc.
英文描述: 128M bits DDR SDRAM
中文描述: 128兆位DDR SDRAM內(nèi)存
文件頁數(shù): 10/51頁
文件大?。?/td> 518K
代理商: EDD1232ABBH
EDD1232ABBH
Data Sheet E0874E40 (Ver. 4.0)
10
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
5ns
6ns
7.5ns
Parameter
Symbol
min.
max.
min.
max.
min.
max.
Unit
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
tWPD
4 + BL/2
4 + BL/2
3 + BL/2
tCK
tRPD
BL/2
BL/2
BL/2
tCK
tWRD
3 + BL/2
3 + BL/2
3 + BL/2
tCK
tBSTW
3
3
3
tCK
Burst stop command to DQ High-Z
tBSTZ
3
3
3
3
3
3
tCK
Read command to write command
delay (to output all data)
tRWD
3 + BL/2
3 + BL/2
3 + BL/2
tCK
Pre-charge command to High-Z
tHZP
3
3
3
3
3
3
tCK
Write command to data in latency
tWCD
1
1
1
1
1
1
tCK
Write recovery time
tWR
3
3
2
tCK
DM to data in latency
tDMD
0
0
0
0
0
0
tCK
Self refresh exit to non-read command tSNR
12
12
12
tCK
Self refresh exit to read command
tSRD
200
200
200
tCK
Power down entry
tPDEN
1
1
1
1
1
1
tCK
Power down exit to command input
tPDEX
2tCK + tIS
2tCK + tIS
2tCK + tIS
tCK
Active to Precharge command period
tRAS
8
7
6
tCK
Active to Active/Auto refresh command
period
Auto refresh to Active/Auto refresh
command period
tRC
12
10
8
tCK
tRFC
14
12
10
tCK
Active to Read delay
tRCDRD
4
3
3
tCK
Active to Write delay
tRCDWR
2
2
2
tCK
Precharge to active command period
tRP
4
3
3
tCK
Auto precharge write recovery and
precharge time
tDAL
7
6
6
tCK
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