參數(shù)資料
型號: EDD1232ABBH-5C-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits DDR SDRAM
中文描述: 4M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝: ROHS COMPLIANT, FBGA-144
文件頁數(shù): 30/51頁
文件大?。?/td> 518K
代理商: EDD1232ABBH-5C-E
EDD1232ABBH
Data Sheet E0874E40 (Ver. 4.0)
30
A Write command to the consecutive Write command Interval
Destination row of the consecutive write
command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCDWR after the ACT command,
the consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCDWR after the ACT
command, the consecutive write command can be issued.
2. Same
3. Different
Any
ACTIVE
IDLE
inA0 inA1 inB0 inB1 inB2 inB3
CK
/CK
Address
BA
DQ
Command
t0
tn+1
tn
tn+2
tn+3
tn+4
tn+5
tn+6
Bank0
Active
BL = 4
Bank0
NOP
DQS
ACT
NOP
WRIT
Row
Column A
WRIT
Column B
Column = A
Write
Column = B
Write
WRITE to WRITE Command Interval (same ROW address in the same bank)
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相關代理商/技術參數(shù)
參數(shù)描述
EDD1232ACBH 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
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EDD1232ACBH-6B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1232ACBH-6B-F 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM
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