- 您現在的位置：買賣IC網 > PDF目錄384277 > EDD1232ABBH-5C-E (ELPIDA MEMORY INC) 128M bits DDR SDRAM PDF資料下載
參數資料
| 型號： | EDD1232ABBH-5C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M bits DDR SDRAM |
| 中文描述： | 4M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, FBGA-144 |
| 文件頁數： | 25/51頁 |
| 文件大?。?/td> | 518K |
| 代理商： | EDD1232ABBH-5C-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
EDD1232ABBH
Data Sheet E0874E40 (Ver. 4.0)
25
CK
/CK
VTT
VTT
DQS
DQ
CL = 3
Command
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
out0
out1
out2
out3
tRPST
tAC,tDQSCK
READ
NOP
tRPRE
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPREH prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling
edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last
low period of DQS is referred as write postamble.
in1
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
t1
t0
t4
t4.5
t5
t6
t7
t8
t9
in0
ACT
NOP
NOP
NOP
WRITE
tWPREH
tWPRES
Row
Column
tRCDWR
tWPST
Write Operation
相關PDF資料 |
PDF描述 |
|---|---|
| EDD2504AKTA-6B-E | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA-7A-E | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA-6B | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA-7A | 256M bits DDR SDRAM (64M words x 4 bits) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EDD1232ACBH | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ACBH-5B-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ACBH-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ACBH-6B-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| ED-D15TF-K | 制造商:IXYS Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。