參數(shù)資料
型號(hào)： E720-EDGE720
英文描述： 500 MHz Pin Electronics Driver. Window Comparator. and Load
中文描述： 500兆赫引腳電子驅(qū)動(dòng)器。窗口比較器。和負(fù)載
文件頁數(shù)： 2/31頁
文件大?。?/td> 221K
代理商： E720-EDGE720
10
www .semtech.com
Edge720
TEST AND MEASUREMENT PRODUCTS
Revision 4 / September 24, 2002
When operating PECL at voltage levels above GND, pins 7
and 8 should be bypassed with 0.1
F capacitors to GND
to ensure stability of the comparator inputs.
Comparator DC Accuracy
The DC accuracy of the Edge720’s comparator circuitry is
quantified by the following datasheet specified parameters:
1.
Comparator input offset voltage
2.
Comparator hysteresis
Comparator input offset voltage quantifies the region
around the programmed threshold voltage applied to
CVA(B) at which the voltage applied to VINP will cause the
comparator output to transition states. Or more simply, it
describes how far the actual threshold voltage of the
comparator may deviate from the value which has been
programmed at CVA(B).
Comparator hysteresis quantifies the difference in the
comparator threshold level when the comparator is
triggered by a signal with a positive slope as opposed to
one with a negative slope when the programmed threshold
voltage at CVA(B) is held constant.
In order words,
hysteresis is a measure of the change in threshold voltage
as a function of the comparator output state (see Figure
11).
Typically, hysteresis is used to prevent multiple
comparator output transitions due to slow input slew rates
in a noisy environment. These slower inputs remain in
the transition region for longer periods of time, allowing
noise present to cause repeated threshold crossings.
Figure 11. Hysteresis
Circuit Description (continued)
Comparator Outputs
The comparator outputs QA(*) and QB(*) are open emitter
outputs that can be used to determine where the input
voltage measured at the VINP input is located in relation
to the comparator thresholds, CVA and CVB. These outputs
are normally terminated through a 50
resistor connected
to PECL – 2V. Other possible termination schemes are
discussed in “AN1003-ECL Output Termination
Techniques.” Comparator output functinality is described
in Table 5.
Table 5. Window Comparator Truth Table
Comparator Power Supplies
PECL is the comparator output power supply input that
determines the logic levels of the comparator circuit’s
differential outputs QA(*) and QB(*). When connected to
GND, the comparator outputs will function as standard
ECL outputs. However, by increasing the value of the PECL
input voltage, QA(*) and QB(*) will track the PECL input
voltage and also increase as shown below in Figure 10.
Figure 10. The Influence of the
PECL Input on Comparator Outputs
)
V
(
P
N
I
VA
QB
Q
)
B
(
A
V
C
<
P
N
I
V0
0
)
B
(
A
V
C
>
P
N
I
V1
1
B
V
C
<
P
N
I
V
<
A
V
C1
0
B
V
C
>
P
N
I
V
>
A
V
C0
1
PECL = GND
a
PECL = +3.3V
b
PECL = +5V
c
+5V
+4V
+3V
+2V
+1V
0V
Q
Q*
Q
Q*
Q
Q*
VPECL
Actual Threshold Voltage
Comparator
Input Signal
Programmed Threshold
Voltage
Hysteresis
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