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參數(shù)資料
| 型號： | E720-EDGE720 |
| 英文描述： | 500 MHz Pin Electronics Driver. Window Comparator. and Load |
| 中文描述： | 500兆赫引腳電子驅(qū)動(dòng)器。窗口比較器。和負(fù)載 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 221K |
| 代理商： | E720-EDGE720 |
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Edge720
TEST AND MEASUREMENT PRODUCTS
Revision 4 / September 24, 2002
PIN Descriptions
Circuit Description (continued)
Driver Level Inputs
The DVL and DVH pins are high impedance analog voltage
inputs that establish the driver output levels of a logical
“1” or “0” at DOUT. Due to possible offsets inherent in
the driver, it may be necessary to apply a voltage to DVH
or DVL that is slightly larger in magnitude than the desired
DOUT voltage.
Driver Stability/Compensation
In order to ensure stability, 100 pF chip capacitors (with
good high frequency characteristics) should be connected
between the DVH and DVH_CAP, as well as between DVL
and DVL_CAP pins. The connectivity of these external
components can be seen in Figure 2.
Figure 2. Driver External Compensation
Component Connectivity
These capacitors are intended to improve the driver output
response to fast changes in the DVL(H) input voltage levels.
Using 100 pF capacitors will allow the DOUT voltage to
track DVL(H) level changes at slew rates up to 400V/
s.
If it is desired to operate the Edge720 in an application
that can tolerate DVL(H) level changes (with the driver
circuit enabled) of less than 100V/
s, these capacitors
can be omitted without any reduction in part performance.
Super Voltage Operation
The Edge720 may be used to drive a super voltage level
of up to 13V at the driver output, DOUT. In order to ensure
that the desired super voltage level is driven, a slightly
higher voltage will need to be switched onto the DVH or
DVL pins to account for possible offsets in the driver.
One Solution that can be used to implement super voltage
functionality is included as a feature on the Edge4707.
The Edge4707B features an analog MUX, which was
designed to switch the driver input voltages between super
voltage and standard levels. Analog MUX connectivity can
be seen below in Figure 3.
Figure 3. Analog MUX Connectivity for
Super Voltage Operation
It is important to note that when driving a super voltage
level, the driver differential input voltage (DVH – DVL) must
be in compliance with the specified range. Connecting
the super voltage inputs (VIHH and VILL) of each analog
MUX to the same super voltage source will ensure this. In
addition, if the Edge720’s comparator and load are
connected to the driver output, as in typical relay-less test
system architecture, they will need to be protected during
super voltage operation as follows:
1. Comparator must be placed in input power down
mode (IPD_C = 1 or SUPERV = 1)
2. Differential load voltage specification
(VLOAD – VCM_IN_A(B)) must be met
3. Load should be disabled (ISK_IN, ISC_IN = 0 mA,
LD_EN < LD_EN*)
Compliance with the precautions above will ensure that
the Edge720 is not inadvertently damaged during super
voltage operation.
1
0
1
0
DVH
DVL
DOUT
VIHH
VIH
VILL
VIL
SV_SEL
Edge720
(Driver Section)
Edge4707
(Analog Mux Section)
High Level Voltage
Low Level Voltage
DVH_CAP
DOUT
DVL_CAP
DVH
DVL
100 pF
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