參數(shù)資料
型號: DZPD6722VCCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: ISA-to-PC-Card (PCMCIA) Controllers
中文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: LQFP-208
文件頁數(shù): 72/138頁
文件大小: 723K
代理商: DZPD6722VCCE
PD6710/
22
ISA-to-PC-Card (PCMCIA) Controllers
72
Datasheet
10.2
FIFO Control
Bit 7
Empty Write FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to
1
, all data in
the FIFO is lost. During read operations when this bit is
1
, the FIFO is empty. During read
operations when this bit is
0
, data is still in the FIFO. This bit is used to ensure the FIFO is empty
before changing timing registers.
FIFO contents will be lost whenever any of the following occur:
PWRGOOD pin (
Table 1
) is
0
.
The card is removed.
V
CC
Power bit (see
Bit 4
VCC Power
on page 50
) is programmed to
0
.
10.3
Misc Control 2
Register Name:
FIFO Control
Index:
17h
Register Per:
socket
Register Compatibility Type:
ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Empty Write
FIFO
Scratchpad Bits
a
a.
RW
RW:0000000
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
Value
I/O Read
I/O Write
0
FIFO not empty
No operation occurs; default on reset
1
FIFO empty
Flush the FIFO
Register Name:
Misc Control 2
Index:
1Eh
Register Per:
chip
Register Compatibility Type:
ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ15 Is RI
Out
DMA System
(PD6722)
Three-State
Bit 7
Drive LED
Enable
5V Core
Suspend
Low-Power
Dynamic
Mode
Bypass
Frequency
Synthesizer
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:1
RW:0
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