參數(shù)資料
型號： DZPD6722VCCE
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： ISA-to-PC-Card (PCMCIA) Controllers
中文描述： PCMCIA BUS CONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 104/138頁
文件大?。?/td> 723K
代理商： DZPD6722VCCE
PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
104
Datasheet
16.3
AC
Timing Specifications
This section includes system timing requirements for the PD67XX. Timings are provided in
nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0
°
C to 70
°
C,
and V
CC
varying from 3.0 to 3.6 V or 4.5 to 5.5 V DC. The AT bus speed is 10 MHz unless
otherwise noted. Note that an asterisk (*) denotes an active-low signal for the ISA bus interface,
and a dash (-) denotes an active-low signal for the PC Card socket interface.
Additionally, the following statements are true for all timing information:
All timings assume a load of 50 pF.
TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold.
16.4
ISA Bus Timing
Table 25. List of AC Timing Specifications
Title
Page Number
Table 26
“
ISA Bus Timing
”
104
Table 27
“
Reset Timing
”
107
Table 28
“
Pulse Mode Interrupt Timing
”
107
Table 29
“
General-Purpose Strobe Timing
”
108
Table 30
“
Input Clock Specification
”
108
Table 31
“
Memory Read/Write Timing (Word Access)
”
111
Table 32
“
Word I/O Read/Write Timing
”
112
Table 33
“
PC Card Read/Write Timing when System Is 8-Bit
”
113
Table 34
“
Normal Byte Read/Write Timing
”
114
Table 35
“
16-Bit System to 8-Bit I/O Card: Odd Byte Timing
”
115
Table 36
“
DMA Read Cycle Timing (PD6722 only)
”
116
Table 37
“
DMA Write Cycle Timing (PD6722 only)
”
118
Table 38
“
DMA Request Timing (PD6722 only)
”
119
Table 26. ISA Bus Timing
(Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Unit
t
1
MEMCS16* active delay from LA[23:17] valid
40
ns
t
1a
LA[23:17] setup to ALE inactive
30
ns
t
1b
LA[23:17] hold from ALE inactive
5
ns
t
2
IOCS16* active delay from SA[15:0]
1
40
ns
1. AEN must be inactive for t
, t
, and t
timing specifications to be applicable.
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
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