參數(shù)資料
型號: DTMFDECODER-RD
廠商: Silicon Laboratories Inc
文件頁數(shù): 28/178頁
文件大?。?/td> 0K
描述: KIT REF DESIGN DTMF DECODER
應(yīng)用說明: DTMF Decoder Ref Design AppNote
標準包裝: 1
主要目的: 電信,DTMF 解碼器
嵌入式:
已用 IC / 零件: C8051F300
主要屬性: 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性: 16 個 Goertzel 濾波器
已供物品: 板,軟件
產(chǎn)品目錄頁面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱: 336-1283
Rev. 2.9
123
C8051F300/1/2/3/4/5
13.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses arbitration or generates a STOP. An SMBus interrupt is generated at the end of
all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating
as a receiver, and after the ACK cycle when operating as a transmitter.
13.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates
the START condition and transmits the first byte containing the address of the target slave and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits
one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the
slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will
switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 13.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any
number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.
A
S
W
P
Data Byte
SLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt
Figure 13.5. Typical Master Transmitter Sequence
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