參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 21/178頁
文件大?。?/td> 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產品目錄頁面： 627 (CN2011-ZH PDF)
相關產品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
SCL
Timer Source
Overflows
SCL High Timeout
T
Low
T
High
Rev. 2.9
117
C8051F300/1/2/3/4/5
Figure 13.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 13.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 13.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
0
Tlow – 4 system clocks
OR
1 system clock + s/w delay*
3 system clocks
1
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.
With the SMBTOE bit set, Timer 2 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “13.3.3. SCL Low Timeout” on page 114). The SMBus interface will force Timer 2
to reload while SCL is high, and allow Timer 2 to count when SCL is low. The Timer 2 interrupt service rou-
tine should be used to reset SMBus communication by disabling and reenabling the SMBus. Timer 2 con-
figuration is described in Section “15.2. Timer 2” on page 151.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 13.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).
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