參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 140/178頁
文件大小： 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
相關產(chǎn)品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
C8051F300/1/2/3/4/5
64
Rev. 2.9
8.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem-
ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca-
tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.3 illustrates the data memory organization of the CIP-51.
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
Figure 8.3. Data Memory Map
8.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.4). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
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DTMH04-2PB 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE DTM HI TEMP B KEY 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, B KEY, 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, B KEY, 2WAY; Series:DTMH; Gender:Receptacle; No. of Contacts:2; No. of Rows:1; Contact Gender:Pin; Connector Mounting:Cable; Connector Shell Size:-; Contact Termination:Crimp; Contact Material:Copper; Contact;RoHS Compliant: Yes
DTMH04-2PC 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE DTM HI TEMP C KEY 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY; Series:DTMH; Gender:Receptacle; No. of Contacts:2; No. of Rows:1; Contact Gender:Pin; Connector Mounting:Cable; Connector Shell Size:-; Contact Termination:Crimp; Contact Material:Copper; Contact;RoHS Compliant: Yes
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