參數(shù)資料
型號(hào)： DSPB56362AG120
廠商： Freescale Semiconductor
文件頁數(shù)： 57/152頁
文件大小： 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 120MHz
非易失內(nèi)存： ROM（126 kB）
芯片上RAM： 42kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
Host Interface (HDI08)
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
2-9
2.7
Host Interface (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The
HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard
microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1
Host Port Configuration
Signal functions associated with the HDI08 vary according to the interface operating mode as determined
by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on
page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on
page Section 6-1.) for descriptions of the other HDI08 configuration registers.
MODD/IRQD
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an
active-low Schmitt-trigger input, internally synchronized to the DSP clock.
MODD/IRQD selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. MODA,
MODB, MODC, and MODD select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is deasserted. If IRQD is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQD to exit the
wait state.
This input is 5 V tolerant.
RESET
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted,
the chip is placed in the reset state and the internal phase generator is
reset. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. If RESET is deasserted
synchronous to CLKOUT, exact start-up timing is guaranteed, allowing
multiple processors to start synchronously and operate together in
“l(fā)ock-step.” When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC, and MODD
inputs. The RESET signal must be asserted during power up. A stable
EXTAL signal must be supplied while RESET is being asserted.
This input is 5 V tolerant.
Table 2-8 Interrupt and Mode Control (continued)
Signal Name
Type
State during Reset
Signal Description
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DSPB56362AG120 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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