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參數(shù)資料
| 型號(hào)： | DSP56F826 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁(yè)數(shù)： | 26/48頁(yè) |
| 文件大小： | 1011K |
| 代理商： | DSP56F826 |
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26
56F826 Technical Data
Figure 13. Connecting an External Clock Signal
Figure 14. External Clock Timing
3.6.4
Phase Locked Loop Timing
Table 11. External Clock Operation Timing Requirements
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
1
1.
2.
3.
4.
See
Figure 13
for details on using the recommended connection of an external clock driver.
When using Time of Day (TOD), maximum external frequency is 6MHz.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
Parameters listed are guaranteed by design.
f
osc
0
4
80
2
MHz
Clock Pulse Width
3,
4
t
PW
6.25
—
—
ns
Table 12. PLL Timing
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
correctly. The PLL is optimized for 4MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and
f
out
/2,
please refer to the OCCS chapter
in the User Manual. ZCLK = f
op
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
f
osc
2
4
6
MHz
PLL output frequency
2
f
out
/2
40
—
110
MHz
PLL stabilization time
3
-40
o
to +85
o
C
t
plls
—
1
10
ms
56F826
XTAL
EXTAL
External
Clock
V
DDA
/2
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F826-827UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual |
| DSP56F826-827UM/D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller |
| DSP56F826BU80 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F826BU80E | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
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