參數(shù)資料
型號(hào)： DSP56F826
廠(chǎng)商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 14/48頁(yè)
文件大?。?/td> 1011K
代理商： DSP56F826
14
56F826 Technical Data
TXD1
(MISO0)
93
Output
Input/Output
Transmit Data (TXD1)
—transmit data output
SPI Master In/Slave Out—
This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if the slave device is not
selected.
After reset, the default state is SCI output.
RXD1
(SS0)
92
Input
(Schmitt)
Input
Receive Data (RXD1)
— receive data input
SPI Slave Select
—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
IRQA
32
Input
(Schmitt)
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor
will exit the Stop state.
IRQB
33
Input
(Schmitt)
External Interrupt Request B
—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can
be programmed to be level-sensitive or negative-edge-triggered. If level-
sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
RESET
45
Input
(Schmitt)
Reset
—This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the Reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the external boot pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
EXTBOOT
25
Input
(Schmitt)
External Boot
—This input is tied to V
DD
to force device to boot from off-
chip memory. Otherwise, it is tied to ground.
Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
Pin No.
Type
Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
DSP56F827E 16-bit Digital Signal Controllers
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DSP56F827FG80E 16-bit Digital Signal Controllers
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參數(shù)描述
DSP56F826-827UM 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:16-Bit Digital Signal Processor Users Manual
DSP56F826-827UM/D 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F826BU80 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F826BU80E 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F826BU80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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