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參數(shù)資料
| 型號： | DSP56F826 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | DSP56F826 |
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10
56F826 Technical Data
PS
29
Output
Program Memory Select
—PS is asserted low for external program
memory access.
DS
28
Output
Data Memory Select
—DS is asserted low for external data memory
access.
RD
26
Output
Read Enable
—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an external
device is enabled onto the device data bus. When RD is deasserted high,
the external data is latched inside the device. When RD is asserted, it
qualifies the A0–A15, PS, and DS pins. RD can be connected directly to
the OE pin of a Static RAM or ROM.
WR
27
Output
Write Enable
—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the device
puts data on the bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it qualifies the
A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of
a Static RAM.
TA0
(GPIOF0)
91
Input/Output
Input/Output
TA0–3
—Timer A Channels 0, 1, 2, and 3
Port F GPIO
—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
After reset, the default state is Quad Timer.
TA1
(GPIOF1)
90
TA2
(GPIOF2)
89
TA3
(GPIOF3)
88
TCK
100
Input
(Schmitt)
Test Clock Input
—This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.
TMS
1
Input
(Schmitt)
Test Mode Select Input
—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
TDI
2
Input
(Schmitt)
Test Data Input
—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-
chip pull-up resistor.
TDO
3
Output
Test Data Output
—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
Pin No.
Type
Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F827E | 16-bit Digital Signal Controllers |
| DSP56F827FG80 | 16-bit Digital Signal Controllers |
| DSP56F827FG80E | 16-bit Digital Signal Controllers |
| DSP56F827 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP8-08AC | Phase-leg Rectifier Diode ISOPLUS220 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F826-827UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual |
| DSP56F826-827UM/D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller |
| DSP56F826BU80 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F826BU80E | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
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