參數(shù)資料
型號： DSP56F826
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁數(shù)： 13/48頁
文件大?。?/td> 1011K
代理商： DSP56F826
Signals and Package Information
56F826 Technical Data
13
SCLK
(GPIOF4)
84
Input/Output
Input/Output
SPI Serial Clock
—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
MOSI
(GPIOF5)
85
Input/Output
Input/Output
SPI Master Out/Slave In (MOSI)
—This serial data pin is an output from a
master device and an input to a slave device. The master device places
data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
MISO
(GPIOF6)
86
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)
—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
SS
(GPIOF7)
87
Input
Input/Output
SPI Slave Select
—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
TXD0
(SCLK0)
97
Output
Input/Output
Transmit Data (TXD0)
—transmit data output
SPI Serial Clock—
In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
RXD0
(MOSI0)
96
Input
Input/
Output
Receive Data (RXD0)
— receive data input
SPI Master Out/Slave In
—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on
the MOSI line one half-cycle before the clock edge the slave device uses
to latch the data.
After reset, the default state is SCI input.
Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
Pin No.
Type
Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
DSP56F827E 16-bit Digital Signal Controllers
DSP56F827FG80 16-bit Digital Signal Controllers
DSP56F827FG80E 16-bit Digital Signal Controllers
DSP56F827 16-bit Hybrid Controller(16位混合控制器)
DSP8-08AC Phase-leg Rectifier Diode ISOPLUS220
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F826-827UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual
DSP56F826-827UM/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F826BU80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
DSP56F826BU80E 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
DSP56F826BU80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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