參數(shù)資料
型號： DSP56321VL275
廠商： Freescale Semiconductor
文件頁數(shù)： 71/84頁
文件大小： 0K
描述： IC DSP 24BIT 275MHZ 196-MAPBGA
標準包裝： 126
系列： DSP56K/Symphony
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 275MHz
非易失內存： ROM（576 B）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-FBGA
供應商設備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
A-9
M_IAL0 EQU 0
; IRQA Mode Interrupt Priority Level (low)
M_IAL1 EQU 1
; IRQA Mode Interrupt Priority Level (high)
M_IAL2 EQU 2
; IRQA Mode Trigger Mode
M_IBL EQU $38
; IRQB Mode Mask
M_IBL0 EQU 3
; IRQB Mode Interrupt Priority Level (low)
M_IBL1 EQU 4
; IRQB Mode Interrupt Priority Level (high)
M_IBL2 EQU 5
; IRQB Mode Trigger Mode
M_ICL EQU $1C0
; IRQC Mode Mask
M_ICL0 EQU 6
; IRQC Mode Interrupt Priority Level (low)
M_ICL1 EQU 7
; IRQC Mode Interrupt Priority Level (high)
M_ICL2 EQU 8
; IRQC Mode Trigger Mode
M_IDL EQU $E00
; IRQD Mode Mask
M_IDL0 EQU 9
; IRQD Mode Interrupt Priority Level (low)
M_IDL1 EQU 10
; IRQD Mode Interrupt Priority Level (high)
M_IDL2 EQU 11
; IRQD Mode Trigger Mode
M_D0L EQU $3000
; DMA0 Interrupt priority Level Mask
M_D0L0 EQU 12
; DMA0 Interrupt Priority Level (low)
M_D0L1 EQU 13
; DMA0 Interrupt Priority Level (high)
M_D1L EQU $C000
; DMA1 Interrupt Priority Level Mask
M_D1L0 EQU 14
; DMA1 Interrupt Priority Level (low)
M_D1L1 EQU 15
; DMA1 Interrupt Priority Level (high)
M_D2L EQU $30000
; DMA2 Interrupt priority Level Mask
M_D2L0 EQU 16
; DMA2 Interrupt Priority Level (low)
M_D2L1 EQU 17
; DMA2 Interrupt Priority Level (high)
M_D3L EQU $C0000
; DMA3 Interrupt Priority Level Mask
M_D3L0 EQU 18
; DMA3 Interrupt Priority Level (low)
M_D3L1 EQU 19
; DMA3 Interrupt Priority Level (high)
M_D4L EQU $300000
; DMA4 Interrupt priority Level Mask
M_D4L0 EQU 20
; DMA4 Interrupt Priority Level (low)
M_D4L1 EQU 21
; DMA4 Interrupt Priority Level (high)
M_D5L EQU $C00000
; DMA5 Interrupt priority Level Mask
M_D5L0 EQU 22
; DMA5 Interrupt Priority Level (low)
M_D5L1 EQU 23
; DMA5 Interrupt Priority Level (high)
;
Interrupt Priority Register Peripheral (IPRP)
M_HPL EQU $3
; Host Interrupt Priority Level Mask
M_HPL0 EQU 0
; Host Interrupt Priority Level (low)
M_HPL1 EQU 1
; Host Interrupt Priority Level (high)
M_S0L EQU $C
; SSI0 Interrupt Priority Level Mask
M_S0L0 EQU 2
; SSI0 Interrupt Priority Level (low)
M_S0L1 EQU 3
; SSI0 Interrupt Priority Level (high)
M_S1L EQU $30
; SSI1 Interrupt Priority Level Mask
M_S1L0 EQU 4
; SSI1 Interrupt Priority Level (low)
M_S1L1 EQU 5
; SSI1 Interrupt Priority Level (high)
M_SCL EQU $C0
; SCI
Interrupt Priority Level
Mask
M_SCL0 EQU 6
; SCI
Interrupt Priority Level
(low)
M_SCL1 EQU 7
; SCI
Interrupt Priority Level
(high)
M_T0L EQU $300
; TIMER Interrupt Priority Level Mask
M_T0L0 EQU 8
; TIMER Interrupt Priority Level (low)
M_T0L1 EQU 9
; TIMER Interrupt Priority Level (high)
;------------------------------------------------------------------------
;
EQUATES for TIMER
;
;------------------------------------------------------------------------
;
Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F
; Timer 0 Control/Status Register
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