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參數(shù)資料
| 型號： | DSP56321VL275 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 7/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 275MHZ 196-MAPBGA |
| 標準包裝： | 126 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 275MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-FBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Host Interface (HI08)
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
1-9
HDS/HDS
HWR/HWR
PB12
Input
Input or Output
Ignored Input
Host Data Strobe—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HDS) following reset.
Host Write Data—When the HI08 is programmed to interface with a double-
data-strobe host bus and the HI function is selected, this signal is the host write
data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HWR) following reset.
Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HREQ/HREQ
HTRQ/HTRQ
PB14
Output
Input or Output
Ignored Input
Host Request—When the HI08 is programmed to interface with a single host
request host bus and the HI function is selected, this signal is the host request
(HREQ) output. The polarity of the host request is programmable but is
configured as active-low (HREQ) following reset. The host request may be
programmed as a driven or open-drain output.
Transmit Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
transmit host request (HTRQ) output. The polarity of the host request is
programmable but is configured as active-low (HTRQ) following reset. The host
request may be programmed as a driven or open-drain output.
Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HACK/HACK
HRRQ/HRRQ
PB15
Input
Output
Input or Output
Ignored Input
Host Acknowledge—When the HI08 is programmed to interface with a single
host request host bus and the HI function is selected, this signal is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable but is configured as active-low (HACK) after
reset.
Receive Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
receive host request (HRRQ) output. The polarity of the host request is
programmable but is configured as active-low (HRRQ) after reset. The host
request may be programmed as a driven or open-drain output.
Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Notes:
1.
In the Stop state, the signal maintains the last state as follows:
If the last state is input, the signal is an ignored input.
If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2.
The Wait processing state does not affect the signal state.
Table 1-10.
Host Interface (Continued)
Signal Name
Type
State During
Reset1,2
Signal Description
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